2 * Copyright (C) 2005 Sandburst Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * Ported from arch/powerpc/cpu/ppc4xx/i2c.c by AS HARNOIS by
26 * Sandburst Corporation.
29 #include <asm/ppc4xx.h>
30 #include <asm/ppc4xx-i2c.h>
33 #include "ppc440gx_i2c.h"
36 #ifdef CONFIG_I2C_BUS1
40 #define IIC_NOK_LA 2 /* Lost arbitration */
41 #define IIC_NOK_ICT 3 /* Incomplete transfer */
42 #define IIC_NOK_XFRA 4 /* Transfer aborted */
43 #define IIC_NOK_DATA 5 /* No data in buffer */
44 #define IIC_NOK_TOUT 6 /* Transfer timeout */
46 #define IIC_TIMEOUT 1 /* 1 second */
47 #if defined(CONFIG_SYS_I2C_NOPROBES)
48 static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
51 static struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_REGISTERS_BUS1_BASE_ADDRESS;
53 static void _i2c_bus1_reset (void)
57 /* Reset status register */
58 /* write 1 in SCMP and IRQA to clear these fields */
59 out_8 (IIC_STS1, 0x0A);
61 /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
62 out_8 (IIC_EXTSTS1, 0x8F);
63 __asm__ volatile ("eieio");
66 * Get current state, reset bus
67 * only if no transfers are pending.
72 status = in_8 (IIC_STS1);
73 udelay (500); /* 500us */
75 } while ((status & IIC_STS_PT) && (i > 0));
76 /* Soft reset controller */
77 status = in_8 (IIC_XTCNTLSS1);
78 out_8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
79 __asm__ volatile ("eieio");
81 /* make sure where in initial state, data hi, clock hi */
82 out_8 (IIC_DIRECTCNTL1, 0xC);
83 for (i = 0; i < 10; i++) {
84 if ((in_8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
85 /* clock until we get to known state */
86 out_8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */
87 udelay (100); /* 100us */
88 out_8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */
89 udelay (100); /* 100us */
94 /* send start condition */
95 out_8 (IIC_DIRECTCNTL1, 0x4);
96 udelay (1000); /* 1ms */
97 /* send stop condition */
98 out_8 (IIC_DIRECTCNTL1, 0xC);
99 udelay (1000); /* 1ms */
100 /* Unreset controller */
101 out_8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
102 udelay (1000); /* 1ms */
105 void i2c1_init (int speed, int slaveadd)
108 unsigned long freqOPB;
111 #ifdef CONFIG_SYS_I2C_INIT_BOARD
112 /* call board specific i2c bus reset routine before accessing the */
113 /* environment, which might be in a chip on that bus. For details */
114 /* about this problem see doc/I2C_Edge_Conditions. */
118 /* Handle possible failed I2C state */
119 /* FIXME: put this into i2c_init_board()? */
122 /* clear lo master address */
123 out_8 (IIC_LMADR1, 0);
125 /* clear hi master address */
126 out_8 (IIC_HMADR1, 0);
128 /* clear lo slave address */
129 out_8 (IIC_LSADR1, 0);
131 /* clear hi slave address */
132 out_8 (IIC_HSADR1, 0);
134 /* Clock divide Register */
135 /* get OPB frequency */
136 get_sys_info (&sysInfo);
137 freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
138 /* set divisor according to freqOPB */
139 divisor = (freqOPB - 1) / 10000000;
142 out_8 (IIC_CLKDIV1, divisor);
145 out_8 (IIC_INTRMSK1, 0);
147 /* clear transfer count */
148 out_8 (IIC_XFRCNT1, 0);
150 /* clear extended control & stat */
151 /* write 1 in SRC SRS SWC SWS to clear these fields */
152 out_8 (IIC_XTCNTLSS1, 0xF0);
154 /* Mode Control Register
155 Flush Slave/Master data buffer */
156 out_8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
157 __asm__ volatile ("eieio");
160 val = in_8(IIC_MDCNTL1);
161 __asm__ volatile ("eieio");
163 /* Ignore General Call, slave transfers are ignored,
164 disable interrupts, exit unknown bus state, enable hold
166 100kHz normaly or FastMode for 400kHz and above
169 val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
170 if( speed >= 400000 ){
171 val |= IIC_MDCNTL_FSM;
173 out_8 (IIC_MDCNTL1, val);
175 /* clear control reg */
176 out_8 (IIC_CNTL1, 0x00);
177 __asm__ volatile ("eieio");
182 This code tries to use the features of the 405GP i2c
183 controller. It will transfer up to 4 bytes in one pass
184 on the loop. It only does out_8(lbz) to the buffer when it
185 is possible to do out16(lhz) transfers.
187 cmd_type is 0 for write 1 for read.
189 addr_len can take any value from 0-255, it is only limited
190 by the char, we could make it larger if needed. If it is
191 0 we skip the address write cycle.
193 Typical case is a Write of an addr followd by a Read. The
194 IBM FAQ does not cover this. On the last byte of the write
195 we don't set the creg CHT bit, and on the first bytes of the
196 read we set the RPST bit.
198 It does not support address only transfers, there must be
199 a data part. If you want to write the address yourself, put
200 it in the data pointer.
202 It does not support transfer to/from address 0.
204 It does not check XFRCNT.
207 int i2c_transfer1(unsigned char cmd_type,
209 unsigned char addr[],
210 unsigned char addr_len,
211 unsigned char data[],
212 unsigned short data_len )
222 if( data == 0 || data_len == 0 ){
223 /*Don't support data transfer of no length or to address 0*/
224 printf( "i2c_transfer: bad call\n" );
227 if( addr && addr_len ){
237 /*Clear Stop Complete Bit*/
238 out_8(IIC_STS1,IIC_STS_SCMP);
243 status = in_8(IIC_STS1);
244 __asm__ volatile("eieio");
246 } while ((status & IIC_STS_PT) && (i>0));
248 if (status & IIC_STS_PT) {
249 result = IIC_NOK_TOUT;
252 /*flush the Master/Slave Databuffers*/
253 out_8(IIC_MDCNTL1, ((in_8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
254 /*need to wait 4 OPB clocks? code below should take that long*/
256 /* 7-bit adressing */
258 out_8(IIC_LMADR1, chip);
259 __asm__ volatile("eieio");
265 while ( tran != cnt && (result == IIC_OK)) {
268 /* Control register =
269 Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
270 Transfer is a sequence of transfers
274 bc = (cnt - tran) > 4 ? 4 :
277 /* if the real cmd type is write continue trans*/
278 if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
279 creg |= IIC_CNTL_CHT;
282 creg |= IIC_CNTL_READ;
284 for(j=0; j<bc; j++) {
286 out_8(IIC_MDBUF1,ptr[tran+j]);
287 __asm__ volatile("eieio");
290 out_8(IIC_CNTL1, creg );
291 __asm__ volatile("eieio");
293 /* Transfer is in progress
294 we have to wait for upto 5 bytes of data
295 1 byte chip address+r/w bit then bc bytes
297 udelay(10) is 1 bit time at 100khz
298 Doubled for slop. 20 is too small.
303 status = in_8(IIC_STS1);
304 __asm__ volatile("eieio");
307 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
310 if (status & IIC_STS_ERR) {
312 status = in_8 (IIC_EXTSTS1);
313 /* Lost arbitration? */
314 if (status & IIC_EXTSTS_LA)
316 /* Incomplete transfer? */
317 if (status & IIC_EXTSTS_ICT)
318 result = IIC_NOK_ICT;
319 /* Transfer aborted? */
320 if (status & IIC_EXTSTS_XFRA)
321 result = IIC_NOK_XFRA;
322 } else if ( status & IIC_STS_PT) {
323 result = IIC_NOK_TOUT;
325 /* Command is reading => get buffer */
326 if ((reading) && (result == IIC_OK)) {
327 /* Are there data in buffer */
328 if (status & IIC_STS_MDBS) {
330 even if we have data we have to wait 4OPB clocks
331 for it to hit the front of the FIFO, after that
332 we can just read. We should check XFCNT here and
333 if the FIFO is full there is no need to wait.
337 ptr[tran+j] = in_8(IIC_MDBUF1);
338 __asm__ volatile("eieio");
341 result = IIC_NOK_DATA;
345 if( ptr == addr && tran == cnt ) {
351 creg = IIC_CNTL_RPST;
357 int i2c_probe1 (uchar chip)
364 * What is needed is to send the chip address and verify that the
365 * address was <ACK>ed (i.e. there was a chip at that address which
366 * drove the data line low).
368 return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
372 int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
378 printf ("I2C read: addr len %d not supported\n", alen);
383 xaddr[0] = (addr >> 24) & 0xFF;
384 xaddr[1] = (addr >> 16) & 0xFF;
385 xaddr[2] = (addr >> 8) & 0xFF;
386 xaddr[3] = addr & 0xFF;
390 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
392 * EEPROM chips that implement "address overflow" are ones
393 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
394 * address and the extra bits end up in the "chip address"
395 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
396 * four 256 byte chips.
398 * Note that we consider the length of the address field to
399 * still be one byte because the extra address bits are
400 * hidden in the chip address.
403 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
405 if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
406 printf( "I2c read: failed %d\n", ret);
412 int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
417 printf ("I2C write: addr len %d not supported\n", alen);
422 xaddr[0] = (addr >> 24) & 0xFF;
423 xaddr[1] = (addr >> 16) & 0xFF;
424 xaddr[2] = (addr >> 8) & 0xFF;
425 xaddr[3] = addr & 0xFF;
428 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
430 * EEPROM chips that implement "address overflow" are ones
431 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
432 * address and the extra bits end up in the "chip address"
433 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
434 * four 256 byte chips.
436 * Note that we consider the length of the address field to
437 * still be one byte because the extra address bits are
438 * hidden in the chip address.
441 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
444 return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
447 /*-----------------------------------------------------------------------
450 uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
454 i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);
459 /*-----------------------------------------------------------------------
462 void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
464 i2c_write1(i2c_addr, reg, 1, &val, 1);
468 int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
471 #if defined(CONFIG_SYS_I2C_NOPROBES)
475 puts ("Valid chip addresses:");
476 for(j = 0; j < 128; j++) {
477 #if defined(CONFIG_SYS_I2C_NOPROBES)
479 for (k = 0; k < sizeof(i2c_no_probes); k++){
480 if (j == i2c_no_probes[k]){
488 if(i2c_probe1(j) == 0) {
494 #if defined(CONFIG_SYS_I2C_NOPROBES)
495 puts ("Excluded chip addresses:");
496 for( k = 0; k < sizeof(i2c_no_probes); k++ )
497 printf(" %02X", i2c_no_probes[k] );
505 iprobe1, 1, 1, do_i2c1_probe,
506 "probe to discover valid I2C chip addresses",
510 #endif /* CONFIG_I2C_BUS1 */