2 * Copyright (C) 2005 Sandburst Corporation
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include "karef_version.h"
29 #include <asm/processor.h>
31 #include <spd_sdram.h>
33 #include "../common/sb_common.h"
34 #include "../common/ppc440gx_i2c.h"
38 void fpga_init (void);
40 KAREF_BOARD_ID_ST board_id_as[] =
42 {"Undefined"}, /* Not specified */
43 {"Kamino Reference Design"},
44 {"Reserved"}, /* Reserved for future use */
45 {"Reserved"}, /* Reserved for future use */
48 KAREF_BOARD_ID_ST ofem_board_id_as[] =
57 /*************************************************************************
60 * Setup chip selects, initialize the Opto-FPGA, initialize
61 * interrupt polarity and triggers.
63 ************************************************************************/
64 int board_early_init_f (void)
66 ppc440_gpio_regs_t *gpio_regs;
68 /* Enable GPIO interrupts */
69 mtsdr(sdr_pfc0, 0x00103E00);
71 /* Setup access for LEDs, and system topology info */
72 gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
73 gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
74 gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
76 /* Turn on all the leds for now */
77 gpio_regs->out = SBCOMMON_GPIO_LEDS;
79 /*--------------------------------------------------------------------+
80 | Initialize EBC CONFIG
81 +-------------------------------------------------------------------*/
83 EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
84 EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
85 EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
86 EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
89 /*--------------------------------------------------------------------+
90 | 1/2 MB FLASH. Initialize bank 0 with default values.
91 +-------------------------------------------------------------------*/
93 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
94 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
95 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
96 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
97 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
98 EBC_BXAP_PEN_DISABLED);
100 mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
101 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
102 /*--------------------------------------------------------------------+
103 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
104 +-------------------------------------------------------------------*/
106 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
107 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
108 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
109 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
110 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
111 EBC_BXAP_PEN_DISABLED);
113 mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
114 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
116 /*--------------------------------------------------------------------+
117 | Compact Flash, uses 2 Chip Selects (2 & 6)
118 +-------------------------------------------------------------------*/
120 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
121 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
122 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
123 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
124 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
125 EBC_BXAP_PEN_DISABLED);
127 mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
128 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
130 /*--------------------------------------------------------------------+
131 | KaRef Scan FPGA. Initialize bank 3 with default values.
132 +-------------------------------------------------------------------*/
134 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
135 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
136 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
137 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
138 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
140 mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
141 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
143 /*--------------------------------------------------------------------+
144 | MAC A & B for Kamino. OFEM FPGA decodes the addresses
145 | Initialize bank 4 with default values.
146 +-------------------------------------------------------------------*/
148 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
149 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
150 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
151 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
152 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
154 mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
155 EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
157 /*--------------------------------------------------------------------+
158 | OFEM FPGA Initialize bank 5 with default values.
159 +-------------------------------------------------------------------*/
161 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
162 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
163 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
164 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
165 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
168 mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
169 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
172 /*--------------------------------------------------------------------+
173 | Compact Flash, uses 2 Chip Selects (2 & 6)
174 +-------------------------------------------------------------------*/
176 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
177 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
178 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
179 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
180 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
181 EBC_BXAP_PEN_DISABLED);
183 mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
184 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
186 /*--------------------------------------------------------------------+
187 | BME-32. Initialize bank 7 with default values.
188 +-------------------------------------------------------------------*/
190 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
191 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
192 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
193 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
194 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
196 mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
197 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
200 /*--------------------------------------------------------------------+
201 * Setup the interrupt controller polarities, triggers, etc.
202 +-------------------------------------------------------------------*/
203 mtdcr (uic0sr, 0xffffffff); /* clear all */
204 mtdcr (uic0er, 0x00000000); /* disable all */
205 mtdcr (uic0cr, 0x00000000); /* all non- critical */
206 mtdcr (uic0pr, 0xfffffe03); /* polarity */
207 mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
208 mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
209 mtdcr (uic0sr, 0xffffffff); /* clear all */
211 mtdcr (uic1sr, 0xffffffff); /* clear all */
212 mtdcr (uic1er, 0x00000000); /* disable all */
213 mtdcr (uic1cr, 0x00000000); /* all non-critical */
214 mtdcr (uic1pr, 0xffffc8ff); /* polarity */
215 mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
216 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
217 mtdcr (uic1sr, 0xffffffff); /* clear all */
219 mtdcr (uic2sr, 0xffffffff); /* clear all */
220 mtdcr (uic2er, 0x00000000); /* disable all */
221 mtdcr (uic2cr, 0x00000000); /* all non-critical */
222 mtdcr (uic2pr, 0xffff83ff); /* polarity */
223 mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
224 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
225 mtdcr (uic2sr, 0xffffffff); /* clear all */
227 mtdcr (uicb0sr, 0xfc000000); /* clear all */
228 mtdcr (uicb0er, 0x00000000); /* disable all */
229 mtdcr (uicb0cr, 0x00000000); /* all non-critical */
230 mtdcr (uicb0pr, 0xfc000000);
231 mtdcr (uicb0tr, 0x00000000);
232 mtdcr (uicb0vr, 0x00000001);
240 /*************************************************************************
243 * Dump pertinent info to the console
245 ************************************************************************/
246 int checkboard (void)
249 unsigned char brd_rev, brd_id;
250 unsigned short sernum;
251 unsigned char scan_rev, scan_id, ofem_rev, ofem_id;
252 unsigned char ofem_brd_rev, ofem_brd_id;
253 KAREF_FPGA_REGS_ST *karef_ps;
254 OFEM_FPGA_REGS_ST *ofem_ps;
256 karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
257 ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
259 scan_id = (unsigned char)((karef_ps->revision_ul &
260 SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
261 >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
263 scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
264 >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
266 brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
267 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
269 brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
270 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
272 ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
273 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
275 ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
276 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
278 if (0xF != ofem_brd_id) {
279 ofem_id = (unsigned char)((ofem_ps->revision_ul &
280 SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
281 >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
283 ofem_rev = (unsigned char)((ofem_ps->revision_ul &
284 SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
285 >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
288 get_sys_info (&sysinfo);
290 sernum = sbcommon_get_serial_number();
292 printf ("Board: Sandburst Corporation Kamino Reference Design "
293 "Serial Number: %d\n", sernum);
294 printf ("%s\n", KAREF_U_BOOT_REL_STR);
296 printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
297 if (sbcommon_get_master()) {
298 printf("Slot 0 - Master\nSlave board");
299 if (sbcommon_secondary_present())
300 printf(" present\n");
302 printf(" not detected\n");
304 printf("Slot 1 - Slave\n\n");
307 printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev);
308 printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id);
309 if(0xF != ofem_brd_id) {
310 printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev);
311 printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev);
314 printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
315 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
316 printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
317 printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
318 printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
320 /* Fix the ack in the bme 32 */
322 out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
330 /*************************************************************************
333 * Initialize I2C bus one to gain access to the fans
335 ************************************************************************/
336 int misc_init_f (void)
338 /* Turn on i2c bus 1 */
340 i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
343 /* Turn on fans 3 & 4 */
348 /*************************************************************************
353 ************************************************************************/
354 int misc_init_r (void)
356 unsigned short sernum;
358 KAREF_FPGA_REGS_ST *karef_ps;
359 OFEM_FPGA_REGS_ST *ofem_ps;
360 unsigned char ofem_id;
362 if(NULL != getenv("secondserial")) {
363 puts("secondserial is set, switching to second serial port\n");
364 setenv("stderr", "serial1");
365 setenv("stdout", "serial1");
366 setenv("stdin", "serial1");
369 setenv("ubrelver", KAREF_U_BOOT_REL_STR);
371 memset(envstr, 0, 255);
372 sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
373 setenv("bldstr", envstr);
376 if( getenv("autorecover")) {
377 setenv("autorecover", NULL);
379 sernum = sbcommon_get_serial_number();
381 printf("\nSetting up environment for automatic filesystem recovery\n");
383 * Setup default bootargs
385 memset(envstr, 0, 255);
387 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
388 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
390 setenv("bootargs", envstr);
393 * Setup Default boot command
395 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
396 "fatload ide 0 8100000 pramdisk;"
397 "bootm 8000000 8100000");
399 printf("Done. Please type allow the system to continue to boot\n");
402 if( getenv("fakeled")) {
403 karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
404 ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
405 ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
406 karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
407 setenv("bootdelay", "-1");
409 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
421 /*************************************************************************
426 ************************************************************************/
427 #ifdef CONFIG_IDE_RESET
428 void ide_set_reset(int on)
430 KAREF_FPGA_REGS_ST *karef_ps;
431 /* TODO: ide reset */
432 karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
435 karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
437 karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
440 #endif /* CONFIG_IDE_RESET */
442 /*************************************************************************
447 ************************************************************************/
450 KAREF_FPGA_REGS_ST *karef_ps;
451 OFEM_FPGA_REGS_ST *ofem_ps;
452 unsigned char ofem_id;
455 /* Ensure we have power all around */
458 karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
460 SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
461 SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
462 SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
463 SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
464 SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
465 SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
466 SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
467 SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
468 SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
470 karef_ps->reset_ul = tmp;
473 * Wait a bit to allow the ofem fpga to get its brains
478 * Check to see if the ofem is there
480 ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
481 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
484 SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
485 SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
486 SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
488 ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
489 ofem_ps->reset_ul = tmp;
491 ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
494 karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
503 int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
505 unsigned short sernum;
508 sernum = sbcommon_get_serial_number();
510 memset(envstr, 0, 255);
512 * Setup our ip address
514 sprintf(envstr, "10.100.70.%d", sernum);
516 setenv("ipaddr", envstr);
518 * Setup the host ip address
520 setenv("serverip", "10.100.17.10");
523 * Setup default bootargs
525 memset(envstr, 0, 255);
527 sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
528 "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
529 "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
530 "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
531 sernum, sernum, sernum);
533 setenv("bootargs_nfs", envstr);
534 setenv("bootargs", envstr);
539 memset(envstr, 0, 255);
541 sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
542 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
545 setenv("bootargs_cf", envstr);
548 * Setup Default boot command
550 setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
551 setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
554 * Setup compact flash boot command
556 setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
564 int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
566 unsigned short sernum;
569 sernum = sbcommon_get_serial_number();
571 printf("\nSetting up environment for filesystem recovery\n");
573 * Setup default bootargs
575 memset(envstr, 0, 255);
577 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
578 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
580 setenv("bootargs", envstr);
583 * Setup Default boot command
586 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
587 "fatload ide 0 8100000 pramdisk;"
588 "bootm 8000000 8100000");
590 printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
591 " please type fsrecover.sh<cr>\n");
602 U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
603 "kasetup - Set environment to factory defaults\n", NULL);
605 U_BOOT_CMD(karecover, 1, 1, karefRecover,
606 "karecover - Set environment to allow for fs recovery\n", NULL);