3 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include "metrobox_version.h"
28 #include <asm/processor.h>
30 #include <spd_sdram.h>
32 #include "../common/ppc440gx_i2c.h"
33 #include "../common/sb_common.h"
35 void fpga_init (void);
37 METROBOX_BOARD_ID_ST board_id_as[] =
38 { {"Undefined"}, /* Not specified */
39 {"2x10Gb"}, /* 2 ports, 10 GbE */
40 {"20x1Gb"}, /* 20 ports, 1 GbE */
41 {"Reserved"}, /* Reserved for future use */
44 /*************************************************************************
47 * Setup chip selects, initialize the Opto-FPGA, initialize
48 * interrupt polarity and triggers.
49 ************************************************************************/
50 int board_early_init_f (void)
52 ppc440_gpio_regs_t *gpio_regs;
54 /* Enable GPIO interrupts */
55 mtsdr(sdr_pfc0, 0x00103E00);
57 /* Setup access for LEDs, and system topology info */
58 gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
59 gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
60 gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
62 /* Turn on all the leds for now */
63 gpio_regs->out = SBCOMMON_GPIO_LEDS;
65 /*--------------------------------------------------------------------+
66 | Initialize EBC CONFIG
67 +-------------------------------------------------------------------*/
69 EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
70 EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
71 EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
72 EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
75 /*--------------------------------------------------------------------+
76 | 1/2 MB FLASH. Initialize bank 0 with default values.
77 +-------------------------------------------------------------------*/
79 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
80 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
81 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
82 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
83 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
84 EBC_BXAP_PEN_DISABLED);
86 mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
87 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
88 /*--------------------------------------------------------------------+
89 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
90 +-------------------------------------------------------------------*/
92 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
93 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
94 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
95 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
96 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
97 EBC_BXAP_PEN_DISABLED);
99 mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
100 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
102 /*--------------------------------------------------------------------+
103 | Compact Flash, uses 2 Chip Selects (2 & 6)
104 +-------------------------------------------------------------------*/
106 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
107 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
108 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
109 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
110 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
111 EBC_BXAP_PEN_DISABLED);
113 mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
114 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
116 /*--------------------------------------------------------------------+
117 | OPTO & OFEM FPGA. Initialize bank 3 with default values.
118 +-------------------------------------------------------------------*/
120 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
121 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
122 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
123 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
124 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
126 mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
127 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
129 /*--------------------------------------------------------------------+
131 | MAC A & B for Kamino. OFEM FPGA decodes the addresses
132 | Initialize bank 4 with default values.
133 +-------------------------------------------------------------------*/
135 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
136 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
137 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
138 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
139 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
141 mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
142 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
144 /*--------------------------------------------------------------------+
145 | Metrobox MAC B Initialize bank 5 with default values.
146 | KA REF FPGA Initialize bank 5 with default values.
147 +-------------------------------------------------------------------*/
149 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
150 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
151 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
152 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
153 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
155 mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
156 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
158 /*--------------------------------------------------------------------+
159 | Compact Flash, uses 2 Chip Selects (2 & 6)
160 +-------------------------------------------------------------------*/
162 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
163 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
164 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
165 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
166 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
167 EBC_BXAP_PEN_DISABLED);
169 mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
170 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
172 /*--------------------------------------------------------------------+
173 | BME-32. Initialize bank 7 with default values.
174 +-------------------------------------------------------------------*/
176 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
177 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
178 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
179 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
180 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
182 mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
183 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
185 /*--------------------------------------------------------------------+
186 * Setup the interrupt controller polarities, triggers, etc.
187 +-------------------------------------------------------------------*/
188 mtdcr (uic0sr, 0xffffffff); /* clear all */
189 mtdcr (uic0er, 0x00000000); /* disable all */
190 mtdcr (uic0cr, 0x00000000); /* all non- critical */
191 mtdcr (uic0pr, 0xfffffe03); /* polarity */
192 mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
193 mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
194 mtdcr (uic0sr, 0xffffffff); /* clear all */
196 mtdcr (uic1sr, 0xffffffff); /* clear all */
197 mtdcr (uic1er, 0x00000000); /* disable all */
198 mtdcr (uic1cr, 0x00000000); /* all non-critical */
199 mtdcr (uic1pr, 0xffffc8ff); /* polarity */
200 mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
201 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
202 mtdcr (uic1sr, 0xffffffff); /* clear all */
204 mtdcr (uic2sr, 0xffffffff); /* clear all */
205 mtdcr (uic2er, 0x00000000); /* disable all */
206 mtdcr (uic2cr, 0x00000000); /* all non-critical */
207 mtdcr (uic2pr, 0xffff83ff); /* polarity */
208 mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
209 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
210 mtdcr (uic2sr, 0xffffffff); /* clear all */
212 mtdcr (uicb0sr, 0xfc000000); /* clear all */
213 mtdcr (uicb0er, 0x00000000); /* disable all */
214 mtdcr (uicb0cr, 0x00000000); /* all non-critical */
215 mtdcr (uicb0pr, 0xfc000000);
216 mtdcr (uicb0tr, 0x00000000);
217 mtdcr (uicb0vr, 0x00000001);
224 /*************************************************************************
227 * Dump pertinent info to the console
228 ************************************************************************/
229 int checkboard (void)
232 unsigned char brd_rev, brd_id;
233 unsigned short sernum;
234 unsigned char opto_rev, opto_id;
235 OPTO_FPGA_REGS_ST *opto_ps;
237 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
239 opto_rev = (unsigned char)((opto_ps->revision_ul &
240 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
241 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
243 opto_id = (unsigned char)((opto_ps->revision_ul &
244 SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
245 >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
247 brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
248 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
249 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
251 brd_id = (unsigned char)((opto_ps->boardinfo_ul &
252 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
253 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
255 get_sys_info (&sysinfo);
257 sernum = sbcommon_get_serial_number();
258 printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
259 printf ("%s\n", METROBOX_U_BOOT_REL_STR);
261 printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
262 if (sbcommon_get_master()) {
263 printf("Slot 0 - Master\nSlave board");
264 if (sbcommon_secondary_present())
265 printf(" present\n");
267 printf(" not detected\n");
269 printf("Slot 1 - Slave\n\n");
272 printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
273 printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]);
275 printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
276 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
277 printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
278 printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
279 printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
282 /* Fix the ack in the bme 32 */
284 out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
291 /*************************************************************************
294 * Initialize I2C bus one to gain access to the fans
295 ************************************************************************/
296 int misc_init_f (void)
298 /* Turn on i2c bus 1 */
300 i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
309 /*************************************************************************
313 ************************************************************************/
314 int misc_init_r (void)
316 unsigned short sernum;
318 unsigned char opto_rev;
319 OPTO_FPGA_REGS_ST *opto_ps;
321 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
323 if(NULL != getenv("secondserial")) {
324 puts("secondserial is set, switching to second serial port\n");
325 setenv("stderr", "serial1");
326 setenv("stdout", "serial1");
327 setenv("stdin", "serial1");
330 setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
332 memset(envstr, 0, 255);
333 sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
334 setenv("bldstr", envstr);
337 if( getenv("autorecover")) {
338 setenv("autorecover", NULL);
340 sernum = sbcommon_get_serial_number();
342 printf("\nSetting up environment for automatic filesystem recovery\n");
344 * Setup default bootargs
346 memset(envstr, 0, 255);
347 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
348 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
350 setenv("bootargs", envstr);
353 * Setup Default boot command
355 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
356 "fatload ide 0 8100000 pramdisk;"
357 "bootm 8000000 8100000");
359 printf("Done. Please type allow the system to continue to boot\n");
362 if( getenv("fakeled")) {
363 setenv("bootdelay", "-1");
365 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
366 opto_rev = (unsigned char)((opto_ps->revision_ul &
367 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
368 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
370 if(0x12 <= opto_rev) {
371 opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
378 /*************************************************************************
380 ************************************************************************/
381 #ifdef CONFIG_IDE_RESET
382 void ide_set_reset(int on)
384 OPTO_FPGA_REGS_ST *opto_ps;
385 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
387 if (on) { /* assert RESET */
388 opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
389 } else { /* release RESET */
390 opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
393 #endif /* CONFIG_IDE_RESET */
395 /*************************************************************************
397 ************************************************************************/
400 OPTO_FPGA_REGS_ST *opto_ps;
401 unsigned char opto_rev;
404 /* Ensure we have power all around */
408 * Take appropriate hw bits out of reset
410 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
413 SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
414 SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
415 SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
416 SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
417 SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
418 SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
419 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
420 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
421 SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
422 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
423 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
424 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
425 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
426 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
427 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
428 SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
429 SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
430 SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
431 opto_ps->reset_ul = tmp;
433 * Turn on the 'Slow Blink' for the System Error Led.
434 * Ensure FPGA rev is up to at least rev 0x12
436 opto_rev = (unsigned char)((opto_ps->revision_ul &
437 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
438 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
439 if(0x12 <= opto_rev) {
440 opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
448 int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
450 unsigned short sernum;
453 sernum = sbcommon_get_serial_number();
455 memset(envstr, 0, 255);
457 * Setup our ip address
459 sprintf(envstr, "10.100.60.%d", sernum);
461 setenv("ipaddr", envstr);
463 * Setup the host ip address
465 setenv("serverip", "10.100.17.10");
468 * Setup default bootargs
470 memset(envstr, 0, 255);
472 sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
473 "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
474 "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
475 ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
476 sernum, sernum, sernum);
478 setenv("bootargs_nfs", envstr);
479 setenv("bootargs", envstr);
484 memset(envstr, 0, 255);
485 sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
486 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
489 setenv("bootargs_cf", envstr);
492 * Setup Default boot command
494 setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
495 setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
498 * Setup compact flash boot command
500 setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
508 int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
510 unsigned short sernum;
513 sernum = sbcommon_get_serial_number();
515 printf("\nSetting up environment for filesystem recovery\n");
517 * Setup default bootargs
519 memset(envstr, 0, 255);
520 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
521 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
524 setenv("bootargs", envstr);
527 * Setup Default boot command
529 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
530 "fatload ide 0 8100000 pramdisk;"
531 "bootm 8000000 8100000");
533 printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
534 " please type fsrecover.sh<cr>\n");
539 U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
540 "mbsetup - Set environment to factory defaults\n", NULL);
542 U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
543 "mbrecover - Set environment to allow for fs recovery\n", NULL);