3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/s3c24x0_cpu.h>
35 #if defined(CONFIG_CMD_NAND)
36 #include <linux/mtd/nand.h>
39 DECLARE_GLOBAL_DATA_PTR;
43 #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
47 #elif FCLK_SPEED==1 /* Fout = 202.8MHz */
65 static inline void delay (unsigned long loops)
67 __asm__ volatile ("1:\n"
69 "bne 1b":"=r" (loops):"0" (loops));
73 * Miscellaneous platform dependent initialisations
78 struct s3c24x0_clock_power * const clk_power =
79 s3c24x0_get_base_clock_power();
80 struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
82 /* to reduce PLL lock time, adjust the LOCKTIME register */
83 clk_power->locktime = 0xFFFFFF;
86 clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
88 /* some delay between MPLL and UPLL */
92 clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
94 /* some delay between MPLL and UPLL */
97 /* set up the I/O ports */
98 gpio->gpacon = 0x007FFFFF;
99 gpio->gpbcon = 0x00044556;
100 gpio->gpbup = 0x000007FF;
101 gpio->gpccon = 0xAAAAAAAA;
102 gpio->gpcup = 0x0000FFFF;
103 gpio->gpdcon = 0xAAAAAAAA;
104 gpio->gpdup = 0x0000FFFF;
105 gpio->gpecon = 0xAAAAAAAA;
106 gpio->gpeup = 0x0000FFFF;
107 gpio->gpfcon = 0x000055AA;
108 gpio->gpfup = 0x000000FF;
109 gpio->gpgcon = 0xFF95FF3A;
110 gpio->gpgup = 0x0000FFFF;
111 gpio->gphcon = 0x0016FAAA;
112 gpio->gphup = 0x000007FF;
114 gpio->extint0 = 0x22222222;
115 gpio->extint1 = 0x22222222;
116 gpio->extint2 = 0x22222222;
118 /* arch number of SMDK2410-Board */
119 gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
121 /* adress of boot parameters */
122 gd->bd->bi_boot_params = 0x30000100;
132 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
133 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
138 #if defined(CONFIG_CMD_NAND)
139 extern ulong nand_probe(ulong physadr);
141 static inline void NF_Reset(void)
146 NF_Cmd(0xFF); /* reset command */
147 for(i = 0; i < 10; i++); /* tWB = 100ns. */
148 NF_WaitRB(); /* wait 200~500us; */
152 static inline void NF_Init(void)
164 NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
165 /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
166 /* 1 1 1 1, 1 xxx, r xxx, r xxx */
167 /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
174 struct s3c2410_nand * const nand = s3c2410_get_base_nand();
178 printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
180 printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
184 #ifdef CONFIG_CMD_NET
185 int board_eth_init(bd_t *bis)
189 rc = cs8900_initialize(0, CONFIG_CS8900_BASE);