2 * sbc8349.c -- WindRiver SBC8349 board support.
3 * Copyright (c) 2006-2007 Wind River Systems, Inc.
5 * Paul Gortmaker <paul.gortmaker@windriver.com>
6 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/mpc8349_pci.h>
36 #if defined(CONFIG_SPD_EEPROM)
37 #include <spd_sdram.h>
39 #if defined(CONFIG_OF_FLAT_TREE)
43 int fixed_sdram(void);
44 void sdram_init(void);
46 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
47 void ddr_enable_ecc(unsigned int dram_size);
50 #ifdef CONFIG_BOARD_EARLY_INIT_F
51 int board_early_init_f (void)
57 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
59 long int initdram (int board_type)
61 volatile immap_t *im = (immap_t *)CFG_IMMR;
64 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
67 puts("Initializing\n");
69 /* DDR SDRAM - Main SODIMM */
70 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
71 #if defined(CONFIG_SPD_EEPROM)
74 msize = fixed_sdram();
77 * Initialize SDRAM if it is on local bus.
81 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
83 * Initialize and enable DDR ECC.
85 ddr_enable_ecc(msize * 1024 * 1024);
88 /* return total bus SDRAM size(bytes) -- DDR */
89 return (msize * 1024 * 1024);
92 #if !defined(CONFIG_SPD_EEPROM)
93 /*************************************************************************
94 * fixed sdram init -- doesn't use serial presence detect.
95 ************************************************************************/
98 volatile immap_t *im = (immap_t *)CFG_IMMR;
103 msize = CFG_DDR_SIZE;
104 for (ddr_size = msize << 20, ddr_size_log2 = 0;
106 ddr_size = ddr_size>>1, ddr_size_log2++) {
111 im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
112 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
114 #if (CFG_DDR_SIZE != 256)
115 #warning Currently any ddr size other than 256 is not supported
117 im->ddr.csbnds[2].csbnds = 0x0000000f;
118 im->ddr.cs_config[2] = CFG_DDR_CONFIG;
120 /* currently we use only one CS, so disable the other banks */
121 im->ddr.cs_config[0] = 0;
122 im->ddr.cs_config[1] = 0;
123 im->ddr.cs_config[3] = 0;
125 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
126 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
130 #if defined(CONFIG_DDR_2T_TIMING)
133 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
134 #if defined (CONFIG_DDR_32BIT)
135 /* for 32-bit mode burst length is 8 */
136 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
138 im->ddr.sdram_mode = CFG_DDR_MODE;
140 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
143 /* enable DDR controller */
144 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
147 #endif/*!CFG_SPD_EEPROM*/
150 int checkboard (void)
152 puts("Board: Wind River SBC834x\n");
157 * if board is fitted with SDRAM
159 #if defined(CFG_BR2_PRELIM) \
160 && defined(CFG_OR2_PRELIM) \
161 && defined(CFG_LBLAWBAR2_PRELIM) \
162 && defined(CFG_LBLAWAR2_PRELIM)
164 * Initialize SDRAM memory on the Local Bus.
167 void sdram_init(void)
169 volatile immap_t *immap = (immap_t *)CFG_IMMR;
170 volatile lbus83xx_t *lbc= &immap->lbus;
171 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
173 puts("\n SDRAM on Local Bus: ");
174 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
177 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
180 /* setup mtrpt, lsrt and lbcr for LB bus */
181 lbc->lbcr = CFG_LBC_LBCR;
182 lbc->mrtpr = CFG_LBC_MRTPR;
183 lbc->lsrt = CFG_LBC_LSRT;
187 * Configure the SDRAM controller Machine Mode Register.
189 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
191 lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
196 lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
223 /* 0x58636733; mode register write operation */
224 lbc->lsdmr = CFG_LBC_LSDMR_4;
229 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
235 void sdram_init(void)
237 puts(" SDRAM on Local Bus: Disabled in config\n");
241 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
245 void ecc_print_status(void)
247 volatile immap_t *immap = (immap_t *)CFG_IMMR;
248 volatile ddr83xx_t *ddr = &immap->ddr;
250 printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
253 printf("Memory Error Interrupt Enable:\n");
254 printf(" Multiple-Bit Error Interrupt Enable: %d\n",
255 (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
256 printf(" Single-Bit Error Interrupt Enable: %d\n",
257 (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
258 printf(" Memory Select Error Interrupt Enable: %d\n\n",
259 (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
262 printf("Memory Error Disable:\n");
263 printf(" Multiple-Bit Error Disable: %d\n",
264 (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
265 printf(" Sinle-Bit Error Disable: %d\n",
266 (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
267 printf(" Memory Select Error Disable: %d\n\n",
268 (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
270 /* Error injection */
271 printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
272 ddr->data_err_inject_hi, ddr->data_err_inject_lo);
274 printf("Memory Data Path Error Injection Mask ECC:\n");
275 printf(" ECC Mirror Byte: %d\n",
276 (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
277 printf(" ECC Injection Enable: %d\n",
278 (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
279 printf(" ECC Error Injection Mask: 0x%02x\n\n",
280 ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
282 /* SBE counter/threshold */
283 printf("Memory Single-Bit Error Management (0..255):\n");
284 printf(" Single-Bit Error Threshold: %d\n",
285 (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
286 printf(" Single-Bit Error Counter: %d\n\n",
287 (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
290 printf("Memory Error Detect:\n");
291 printf(" Multiple Memory Errors: %d\n",
292 (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
293 printf(" Multiple-Bit Error: %d\n",
294 (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
295 printf(" Single-Bit Error: %d\n",
296 (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
297 printf(" Memory Select Error: %d\n\n",
298 (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
301 printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
302 printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
303 ddr->capture_data_hi, ddr->capture_data_lo);
304 printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
305 ddr->capture_ecc & CAPTURE_ECC_ECE);
307 printf("Memory Error Attributes Capture:\n");
308 printf(" Data Beat Number: %d\n",
309 (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
310 printf(" Transaction Size: %d\n",
311 (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
312 printf(" Transaction Source: %d\n",
313 (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
314 printf(" Transaction Type: %d\n",
315 (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
316 printf(" Error Information Valid: %d\n\n",
317 ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
320 int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
322 volatile immap_t *immap = (immap_t *)CFG_IMMR;
323 volatile ddr83xx_t *ddr = &immap->ddr;
325 u64 *addr, count, val64;
329 printf ("Usage:\n%s\n", cmdtp->usage);
334 if (strcmp(argv[1], "status") == 0) {
337 } else if (strcmp(argv[1], "captureclear") == 0) {
338 ddr->capture_address = 0;
339 ddr->capture_data_hi = 0;
340 ddr->capture_data_lo = 0;
341 ddr->capture_ecc = 0;
342 ddr->capture_attributes = 0;
348 if (strcmp(argv[1], "sbecnt") == 0) {
349 val = simple_strtoul(argv[2], NULL, 10);
351 printf("Incorrect Counter value, should be 0..255\n");
355 val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
356 val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
360 } else if (strcmp(argv[1], "sbethr") == 0) {
361 val = simple_strtoul(argv[2], NULL, 10);
363 printf("Incorrect Counter value, should be 0..255\n");
367 val = (val << ECC_ERROR_MAN_SBET_SHIFT);
368 val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
372 } else if (strcmp(argv[1], "errdisable") == 0) {
373 val = ddr->err_disable;
375 if (strcmp(argv[2], "+sbe") == 0) {
376 val |= ECC_ERROR_DISABLE_SBED;
377 } else if (strcmp(argv[2], "+mbe") == 0) {
378 val |= ECC_ERROR_DISABLE_MBED;
379 } else if (strcmp(argv[2], "+mse") == 0) {
380 val |= ECC_ERROR_DISABLE_MSED;
381 } else if (strcmp(argv[2], "+all") == 0) {
382 val |= (ECC_ERROR_DISABLE_SBED |
383 ECC_ERROR_DISABLE_MBED |
384 ECC_ERROR_DISABLE_MSED);
385 } else if (strcmp(argv[2], "-sbe") == 0) {
386 val &= ~ECC_ERROR_DISABLE_SBED;
387 } else if (strcmp(argv[2], "-mbe") == 0) {
388 val &= ~ECC_ERROR_DISABLE_MBED;
389 } else if (strcmp(argv[2], "-mse") == 0) {
390 val &= ~ECC_ERROR_DISABLE_MSED;
391 } else if (strcmp(argv[2], "-all") == 0) {
392 val &= ~(ECC_ERROR_DISABLE_SBED |
393 ECC_ERROR_DISABLE_MBED |
394 ECC_ERROR_DISABLE_MSED);
396 printf("Incorrect err_disable field\n");
400 ddr->err_disable = val;
401 __asm__ __volatile__ ("sync");
402 __asm__ __volatile__ ("isync");
404 } else if (strcmp(argv[1], "errdetectclr") == 0) {
405 val = ddr->err_detect;
407 if (strcmp(argv[2], "mme") == 0) {
408 val |= ECC_ERROR_DETECT_MME;
409 } else if (strcmp(argv[2], "sbe") == 0) {
410 val |= ECC_ERROR_DETECT_SBE;
411 } else if (strcmp(argv[2], "mbe") == 0) {
412 val |= ECC_ERROR_DETECT_MBE;
413 } else if (strcmp(argv[2], "mse") == 0) {
414 val |= ECC_ERROR_DETECT_MSE;
415 } else if (strcmp(argv[2], "all") == 0) {
416 val |= (ECC_ERROR_DETECT_MME |
417 ECC_ERROR_DETECT_MBE |
418 ECC_ERROR_DETECT_SBE |
419 ECC_ERROR_DETECT_MSE);
421 printf("Incorrect err_detect field\n");
425 ddr->err_detect = val;
427 } else if (strcmp(argv[1], "injectdatahi") == 0) {
428 val = simple_strtoul(argv[2], NULL, 16);
430 ddr->data_err_inject_hi = val;
432 } else if (strcmp(argv[1], "injectdatalo") == 0) {
433 val = simple_strtoul(argv[2], NULL, 16);
435 ddr->data_err_inject_lo = val;
437 } else if (strcmp(argv[1], "injectecc") == 0) {
438 val = simple_strtoul(argv[2], NULL, 16);
440 printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
443 val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
445 ddr->ecc_err_inject = val;
447 } else if (strcmp(argv[1], "inject") == 0) {
448 val = ddr->ecc_err_inject;
450 if (strcmp(argv[2], "en") == 0)
451 val |= ECC_ERR_INJECT_EIEN;
452 else if (strcmp(argv[2], "dis") == 0)
453 val &= ~ECC_ERR_INJECT_EIEN;
455 printf("Incorrect command\n");
457 ddr->ecc_err_inject = val;
458 __asm__ __volatile__ ("sync");
459 __asm__ __volatile__ ("isync");
461 } else if (strcmp(argv[1], "mirror") == 0) {
462 val = ddr->ecc_err_inject;
464 if (strcmp(argv[2], "en") == 0)
465 val |= ECC_ERR_INJECT_EMB;
466 else if (strcmp(argv[2], "dis") == 0)
467 val &= ~ECC_ERR_INJECT_EMB;
469 printf("Incorrect command\n");
471 ddr->ecc_err_inject = val;
477 if (strcmp(argv[1], "test") == 0) {
478 addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
479 count = simple_strtoul(argv[3], NULL, 16);
482 printf("Address not alligned on double word boundary\n");
486 disable_interrupts();
489 for (i = addr; i < addr + count; i++) {
491 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
492 __asm__ __volatile__ ("sync");
493 __asm__ __volatile__ ("isync");
495 /* write memory location injecting errors */
496 *i = 0x1122334455667788ULL;
497 __asm__ __volatile__ ("sync");
499 /* disable injects */
500 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
501 __asm__ __volatile__ ("sync");
502 __asm__ __volatile__ ("isync");
504 /* read data, this generates ECC error */
506 __asm__ __volatile__ ("sync");
508 /* disable errors for ECC */
509 ddr->err_disable |= ~ECC_ERROR_ENABLE;
510 __asm__ __volatile__ ("sync");
511 __asm__ __volatile__ ("isync");
513 /* re-initialize memory, write the location again
514 * NOT injecting errors this time */
515 *i = 0xcafecafecafecafeULL;
516 __asm__ __volatile__ ("sync");
518 /* enable errors for ECC */
519 ddr->err_disable &= ECC_ERROR_ENABLE;
520 __asm__ __volatile__ ("sync");
521 __asm__ __volatile__ ("isync");
531 printf ("Usage:\n%s\n", cmdtp->usage);
537 "ecc - support for DDR ECC features\n",
538 "status - print out status info\n"
539 "ecc captureclear - clear capture regs data\n"
540 "ecc sbecnt <val> - set Single-Bit Error counter\n"
541 "ecc sbethr <val> - set Single-Bit Threshold\n"
542 "ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
543 " [-|+]sbe - Single-Bit Error\n"
544 " [-|+]mbe - Multiple-Bit Error\n"
545 " [-|+]mse - Memory Select Error\n"
546 " [-|+]all - all errors\n"
547 "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
548 " mme - Multiple Memory Errors\n"
549 " sbe - Single-Bit Error\n"
550 " mbe - Multiple-Bit Error\n"
551 " mse - Memory Select Error\n"
552 " all - all errors\n"
553 "ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
554 "ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
555 "ecc injectecc <ecc> - set ECC Error Injection Mask\n"
556 "ecc inject <en|dis> - enable/disable error injection\n"
557 "ecc mirror <en|dis> - enable/disable mirror byte\n"
558 "ecc test <addr> <cnt> - test mem region:\n"
559 " - enables injects\n"
560 " - writes pattern injecting errors\n"
561 " - disables injects\n"
562 " - reads pattern back, generates error\n"
565 #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
567 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
569 ft_board_setup(void *blob, bd_t *bd)
575 ft_pci_setup(blob, bd);
577 ft_cpu_setup(blob, bd);
579 p = ft_get_prop(blob, "/memory/reg", &len);
581 *p++ = cpu_to_be32(bd->bi_memstart);
582 *p = cpu_to_be32(bd->bi_memsize);