2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
4 * Copyright 2007 Embedded Specialties, Inc.
6 * Copyright 2004, 2007 Freescale Semiconductor.
8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
33 #include <asm/fsl_pci.h>
34 #include <asm/fsl_ddr_sdram.h>
35 #include <spd_sdram.h>
40 #include <fdt_support.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 void local_bus_init(void);
45 void sdram_init(void);
46 long int fixed_sdram (void);
48 int board_early_init_f (void)
55 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
56 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
58 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
62 * Initialize local bus.
66 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
67 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
72 initdram(int board_type)
76 puts("Initializing\n");
78 #if defined(CONFIG_DDR_DLL)
81 * Work around to stabilize DDR DLL MSYNC_IN.
82 * Errata DDR9 seems to have been fixed.
83 * This is now the workaround for Errata DDR11:
84 * Override DLL = 1, Course Adj = 1, Tap Select = 0
87 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
89 out_be32(&gur->ddrdllcr, 0x81000000);
90 asm("sync;isync;msync");
95 #if defined(CONFIG_SPD_EEPROM)
96 dram_size = fsl_ddr_sdram();
97 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
98 dram_size *= 0x100000;
100 dram_size = fixed_sdram ();
104 * SDRAM Initialization
113 * Initialize Local Bus
118 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
119 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
125 get_sys_info(&sysinfo);
126 clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
127 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
129 out_be32(&gur->lbiuiplldcr1, 0x00078080);
131 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
132 } else if (clkdiv == 8) {
133 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
134 } else if (clkdiv == 4) {
135 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
138 setbits_be32(&lbc->lcrr, 0x00030000);
140 asm("sync;isync;msync");
142 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
143 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
147 * Initialize SDRAM memory on the Local Bus.
152 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
155 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
156 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
161 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
164 * Setup SDRAM Base and Option Registers
166 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
167 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
168 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
169 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
171 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
174 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
175 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
179 * MPC8548 uses "new" 15-16 style addressing.
181 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
182 lsdmr_common |= LSDMR_BSMA1516;
185 * Issue PRECHARGE ALL command.
187 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
190 ppcDcbf((unsigned long) sdram_addr);
194 * Issue 8 AUTO REFRESH commands.
196 for (idx = 0; idx < 8; idx++) {
197 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
200 ppcDcbf((unsigned long) sdram_addr);
205 * Issue 8 MODE-set command.
207 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
210 ppcDcbf((unsigned long) sdram_addr);
214 * Issue NORMAL OP command.
216 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
219 ppcDcbf((unsigned long) sdram_addr);
220 udelay(200); /* Overkill. Must wait > 200 bus cycles */
222 #endif /* enable SDRAM init */
225 #if defined(CONFIG_SYS_DRAM_TEST)
229 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
230 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
233 printf("Testing DRAM from 0x%08x to 0x%08x\n",
234 CONFIG_SYS_MEMTEST_START,
235 CONFIG_SYS_MEMTEST_END);
237 printf("DRAM test phase 1:\n");
238 for (p = pstart; p < pend; p++)
241 for (p = pstart; p < pend; p++) {
242 if (*p != 0xaaaaaaaa) {
243 printf ("DRAM test fails at: %08x\n", (uint) p);
248 printf("DRAM test phase 2:\n");
249 for (p = pstart; p < pend; p++)
252 for (p = pstart; p < pend; p++) {
253 if (*p != 0x55555555) {
254 printf ("DRAM test fails at: %08x\n", (uint) p);
259 printf("DRAM test passed.\n");
264 #if !defined(CONFIG_SPD_EEPROM)
265 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
266 /*************************************************************************
267 * fixed_sdram init -- doesn't use serial presence detect.
268 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
269 ************************************************************************/
270 long int fixed_sdram (void)
272 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
274 out_be32(&ddr->cs0_bnds, 0x0000007f);
275 out_be32(&ddr->cs1_bnds, 0x008000ff);
276 out_be32(&ddr->cs2_bnds, 0x00000000);
277 out_be32(&ddr->cs3_bnds, 0x00000000);
278 out_be32(&ddr->cs0_config, 0x80010101);
279 out_be32(&ddr->cs1_config, 0x80010101);
280 out_be32(&ddr->cs2_config, 0x00000000);
281 out_be32(&ddr->cs3_config, 0x00000000);
282 out_be32(&ddr->timing_cfg_3, 0x00000000);
283 out_be32(&ddr->timing_cfg_0, 0x00220802);
284 out_be32(&ddr->timing_cfg_1, 0x38377322);
285 out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
286 out_be32(&ddr->sdram_cfg, 0x4300C000);
287 out_be32(&ddr->sdram_cfg_2, 0x24401000);
288 out_be32(&ddr->sdram_mode, 0x23C00542);
289 out_be32(&ddr->sdram_mode_2, 0x00000000);
290 out_be32(&ddr->sdram_interval, 0x05080100);
291 out_be32(&ddr->sdram_md_cntl, 0x00000000);
292 out_be32(&ddr->sdram_data_init, 0x00000000);
293 out_be32(&ddr->sdram_clk_cntl, 0x03800000);
294 asm("sync;isync;msync");
297 #if defined (CONFIG_DDR_ECC)
298 /* Enable ECC checking */
299 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
301 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
304 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
309 static struct pci_controller pci1_hose;
310 #endif /* CONFIG_PCI1 */
313 static struct pci_controller pcie1_hose;
314 #endif /* CONFIG_PCIE1 */
321 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
322 struct fsl_pci_info pci_info[2];
323 u32 devdisr, pordevsr, porpllsr, io_sel;
324 int first_free_busno = 0;
331 devdisr = in_be32(&gur->devdisr);
332 pordevsr = in_be32(&gur->pordevsr);
333 porpllsr = in_be32(&gur->porpllsr);
334 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
336 debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
339 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
340 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
341 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
342 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
343 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
345 printf (" PCI host: %d bit, %s MHz, %s, %s\n",
347 (pci_speed == 33000000) ? "33" :
348 (pci_speed == 66000000) ? "66" : "unknown",
349 pci_clk_sel ? "sync" : "async",
350 pci_arb ? "arbiter" : "external-arbiter");
352 SET_STD_PCI_INFO(pci_info[num], 1);
353 first_free_busno = fsl_pci_init_port(&pci_info[num++],
354 &pci1_hose, first_free_busno);
356 printf (" PCI: disabled\n");
361 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
364 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
367 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
369 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
370 SET_STD_PCIE_INFO(pci_info[num], 1);
371 printf (" PCIE at base address %lx\n", pci_info[num].regs);
372 first_free_busno = fsl_pci_init_port(&pci_info[num++],
373 &pcie1_hose, first_free_busno);
375 printf (" PCIE: disabled\n");
380 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
385 int board_eth_init(bd_t *bis)
387 tsec_standard_init(bis);
389 return 0; /* otherwise cpu_eth_init gets run */
392 int last_stage_init(void)
397 #if defined(CONFIG_OF_BOARD_SETUP)
398 void ft_board_setup(void *blob, bd_t *bd)
400 ft_cpu_setup(blob, bd);
402 #ifdef CONFIG_FSL_PCI_INIT