2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
4 * Copyright 2007 Embedded Specialties, Inc.
6 * Copyright 2004, 2007 Freescale Semiconductor.
8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/processor.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_pci.h>
18 #include <fsl_ddr_sdram.h>
19 #include <asm/fsl_serdes.h>
20 #include <spd_sdram.h>
24 #include <linux/libfdt.h>
25 #include <fdt_support.h>
27 void local_bus_init(void);
29 int board_early_init_f (void)
36 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
37 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
39 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
43 * Initialize local bus.
47 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
48 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
53 * Initialize Local Bus
58 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
59 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
61 uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
64 get_sys_info(&sysinfo);
66 lbc_mhz = sysinfo.freq_localbus / 1000000;
67 clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
69 debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
71 out_be32(&gur->lbiuiplldcr1, 0x00078080);
73 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
74 } else if (clkdiv == 8) {
75 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
76 } else if (clkdiv == 4) {
77 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
81 * Local Bus Clock > 83.3 MHz. According to timing
82 * specifications set LCRR[EADC] to 2 delay cycles.
90 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
91 * disable PLL bypass for Local Bus Clock > 83 MHz.
94 lcrr &= (~LCRR_DBYP); /* DLL Enabled */
97 lcrr |= LCRR_DBYP; /* DLL Bypass */
99 out_be32(&lbc->lcrr, lcrr);
100 asm("sync;isync;msync");
103 * According to MPC8548ERMAD Rev.1.3 read back LCRR
104 * and terminate with isync
106 lcrr = in_be32(&lbc->lcrr);
109 /* let DLL stabilize */
112 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
113 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
117 * Initialize SDRAM memory on the Local Bus.
119 void lbc_sdram_init(void)
121 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
124 const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
125 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
126 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
127 uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
131 print_size(size, "\n");
134 * Setup SDRAM Base and Option Registers
136 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
137 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
138 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
139 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
141 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
144 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
145 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
149 * Issue PRECHARGE ALL command.
151 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
154 ppcDcbf((unsigned long) sdram_addr);
156 ppcDcbf((unsigned long) sdram_addr2);
160 * Issue 8 AUTO REFRESH commands.
162 for (idx = 0; idx < 8; idx++) {
163 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
166 ppcDcbf((unsigned long) sdram_addr);
168 ppcDcbf((unsigned long) sdram_addr2);
173 * Issue 8 MODE-set command.
175 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
178 ppcDcbf((unsigned long) sdram_addr);
180 ppcDcbf((unsigned long) sdram_addr2);
184 * Issue RFEN command.
186 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
189 ppcDcbf((unsigned long) sdram_addr);
191 ppcDcbf((unsigned long) sdram_addr2);
192 udelay(200); /* Overkill. Must wait > 200 bus cycles */
194 #endif /* enable SDRAM init */
197 #if defined(CONFIG_SYS_DRAM_TEST)
201 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
202 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
205 printf("Testing DRAM from 0x%08x to 0x%08x\n",
206 CONFIG_SYS_MEMTEST_START,
207 CONFIG_SYS_MEMTEST_END);
209 printf("DRAM test phase 1:\n");
210 for (p = pstart; p < pend; p++)
213 for (p = pstart; p < pend; p++) {
214 if (*p != 0xaaaaaaaa) {
215 printf ("DRAM test fails at: %08x\n", (uint) p);
220 printf("DRAM test phase 2:\n");
221 for (p = pstart; p < pend; p++)
224 for (p = pstart; p < pend; p++) {
225 if (*p != 0x55555555) {
226 printf ("DRAM test fails at: %08x\n", (uint) p);
231 printf("DRAM test passed.\n");
237 static struct pci_controller pci1_hose;
238 #endif /* CONFIG_PCI1 */
244 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
245 int first_free_busno = 0;
248 struct fsl_pci_info pci_info;
249 u32 devdisr = in_be32(&gur->devdisr);
250 u32 pordevsr = in_be32(&gur->pordevsr);
251 u32 porpllsr = in_be32(&gur->porpllsr);
253 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
254 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
255 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
256 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
257 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
259 printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
261 (pci_speed == 33000000) ? "33" :
262 (pci_speed == 66000000) ? "66" : "unknown",
263 pci_clk_sel ? "sync" : "async",
264 pci_arb ? "arbiter" : "external-arbiter");
266 SET_STD_PCI_INFO(pci_info, 1);
267 set_next_law(pci_info.mem_phys,
268 law_size_bits(pci_info.mem_size), pci_info.law);
269 set_next_law(pci_info.io_phys,
270 law_size_bits(pci_info.io_size), pci_info.law);
272 first_free_busno = fsl_pci_init_port(&pci_info,
273 &pci1_hose, first_free_busno);
275 printf("PCI: disabled\n");
280 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
283 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
285 fsl_pcie_init_board(first_free_busno);
289 int board_eth_init(bd_t *bis)
291 tsec_standard_init(bis);
293 return 0; /* otherwise cpu_eth_init gets run */
296 int last_stage_init(void)
301 #if defined(CONFIG_OF_BOARD_SETUP)
302 int ft_board_setup(void *blob, bd_t *bd)
304 ft_cpu_setup(blob, bd);
306 #ifdef CONFIG_FSL_PCI_INIT