1 /*------------------------------------------------------------------------------+
3 * This souce code has been made available to you by EuroDesign
4 * (www.eurodsn.de). It's based on the original IBM source code, so
7 * This source code is dual-licensed. You may use it under the terms of the
8 * GNU General Public License version 2, or under the license below.
10 * This source code has been made available to you by IBM on an AS-IS
11 * basis. Anyone receiving this source is licensed under IBM
12 * copyrights to use it in any way he or she deems fit, including
13 * copying it, modifying it, compiling it, and redistributing it either
14 * with or without modifications. No license under IBM patents or
15 * patent applications is to be implied by the copyright license.
17 * Any user of this software should understand that IBM cannot provide
18 * technical support for this software and will not be responsible for
19 * any consequences resulting from the use of this software.
21 * Any person who transfers this source code or any derivative work
22 * must include the IBM copyright notice, this paragraph, and the
23 * preceding two paragraphs in the transferred software.
25 * COPYRIGHT I B M CORPORATION 1995
26 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
27 *------------------------------------------------------------------------------- */
30 #include <asm/ppc4xx.h>
32 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
34 #include <ppc_asm.tmpl>
37 #include <asm/cache.h>
41 * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
43 * IMPORTANT: For pass1 this code must run from cache since you can not
44 * reliably change a peripheral banks timing register (pbxap) while running
45 * code from that bank. For ex., since we are running from ROM on bank 0, we
46 * can NOT execute the code that modifies bank 0 timings from ROM, so
47 * we run it from cache.
52 * Bank 3 - Second Flash
53 * Bank 4 - USB controller
55 .globl ext_bus_cntlr_init
58 * We need the current boot up configuration to set correct
59 * timings into internal flash and external flash
61 mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
62 0 0 -> 8 bit external ROM
63 0 1 -> 16 bit internal ROM */
65 srw r24,r24,r4 /* shift right r24 two positions */
68 * All calculations are based on 33MHz EBC clock.
70 * First, create a "very slow" timing (~250ns) with burst mode enabled
71 * This is need for the external flash access
74 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
77 * Second, create a fast timing:
78 * 90ns first cycle - 3 clock access
79 * and 90ns burst cycle, plus 1 clock after the last access
80 * This is used for the internal access
83 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
86 * We can't change settings on CS# if we currently use them.
87 * -> load a few instructions into cache and run this code from cache
89 mflr r4 /* save link register */
92 mflr r3 /* get address of ..getAddr */
93 mtlr r4 /* restore link register */
94 addi r4,0,14 /* set ctr to 10; used to prefetch */
95 mtctr r4 /* 10 cache lines to fit this function
96 in cache (gives us 8x10=80 instructions) */
98 icbt r0,r3 /* prefetch cache line for addr in r3 */
99 addi r3,r3,32 /* move to next cache line */
100 bdnz ..ebcloop /* continue for 10 cache lines */
102 * Delay to ensure all accesses to ROM are complete before changing
103 * bank 0 timings. 200usec should be enough.
104 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
107 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
110 bdnz ..spinlp /* spin loop */
112 /*-----------------------------------------------------------------------
113 * Memory Bank 0 (BOOT-ROM) initialization
114 * 0xFFEF00000....0xFFFFFFF
115 * We only have to change the timing. Mapping is ok by boot-strapping
116 *----------------------------------------------------------------------- */
118 li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */
119 mtdcr EBC0_CFGADDR,r4
121 mr r4,r26 /* assume internal fast flash is boot flash */
122 cmpwi r24,0x2000 /* assumption true? ... */
124 mr r4,r25 /* ...no, use the slow variant */
125 mr r25,r26 /* use this for the other flash */
127 mtdcr EBC0_CFGDATA,r4 /* change timing now */
129 li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */
130 mtdcr EBC0_CFGADDR,r4
131 mfdcr r4,EBC0_CFGDATA
133 ori r3,r3,0x8000 /* allow reads and writes */
135 mtdcr EBC0_CFGDATA,r4
137 /*-----------------------------------------------------------------------
138 * Memory Bank 3 (Second-Flash) initialization
139 * 0xF0000000...0xF01FFFFF -> 2MB
140 *----------------------------------------------------------------------- */
142 li r4,PB3AP /* Peripheral Bank 1 Access Parameter */
143 mtdcr EBC0_CFGADDR,r4
144 mtdcr EBC0_CFGDATA,r2 /* change timing */
146 li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */
147 mtdcr EBC0_CFGADDR,r4
152 * Consider boot configuration
154 xori r24,r24,0x2000 /* invert current bus width */
156 mtdcr EBC0_CFGDATA,r4
158 /*-----------------------------------------------------------------------
159 * Memory Bank 1 (NAND-Flash) initialization
160 * 0x77D00000...0x77DFFFFF -> 1MB
161 * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
162 * - the setup time is 0ns
163 * - the hold time is 15ns
171 * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
172 *----------------------------------------------------------------------- */
174 li r4,PB1AP /* Peripheral Bank 1 Access Parameter */
175 mtdcr EBC0_CFGADDR,r4
179 mtdcr EBC0_CFGDATA,r4
181 li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */
182 mtdcr EBC0_CFGADDR,r4
186 mtdcr EBC0_CFGDATA,r4
189 /* USB init (without acceleration) */
190 #ifndef CONFIG_ISP1161_PRESENT
191 li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
192 mtdcr EBC0_CFGADDR,r4
195 mtdcr EBC0_CFGDATA,r4
198 /*-----------------------------------------------------------------------
199 * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
200 * 0x78000000...0x7BFFFFFF -> 64 MB
201 * Wir arbeiten bei 33 MHz -> 30ns
202 *-----------------------------------------------------------------------
204 A7 (ppc notation) or A24 (standard notation) decides about
206 A7/A24=0 -> memory cycle
207 A7/ /A24=1 -> I/O cycle
209 li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */
210 mtdcr EBC0_CFGADDR,r4
212 We emulate an ISA access
215 2. wait 0 EBC clocks -> CSN=0
217 4. wait 0 EBC clock -> OEN/WBN=0
219 6. wait 4 clocks (ca. 90ns) and for Ready signal
220 7. hold for 4 clocks -> TH=4
224 /* faster access to isa-bus */
231 mtdcr EBC0_CFGDATA,r4
233 #ifdef IDE_USES_ISA_EMULATION
234 li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */
235 mtdcr EBC0_CFGADDR,r25
236 mtdcr EBC0_CFGDATA,r4
239 li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */
240 mtdcr EBC0_CFGADDR,r25
241 mtdcr EBC0_CFGDATA,r4
242 li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */
243 mtdcr EBC0_CFGADDR,r25
244 mtdcr EBC0_CFGDATA,r4
246 li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */
247 mtdcr EBC0_CFGADDR,r25
251 mtdcr EBC0_CFGDATA,r4
253 * the other areas are only 1MiB in size
258 li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */
259 mtdcr EBC0_CFGADDR,r25
262 mtdcr EBC0_CFGDATA,r4
264 li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */
265 mtdcr EBC0_CFGADDR,r25
268 mtdcr EBC0_CFGDATA,r4
270 #ifndef CONFIG_ISP1161_PRESENT
271 li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */
272 mtdcr EBC0_CFGADDR,r25
275 mtdcr EBC0_CFGDATA,r4
277 #ifdef IDE_USES_ISA_EMULATION
278 li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */
279 mtdcr EBC0_CFGADDR,r25
282 mtdcr EBC0_CFGDATA,r4
285 /*-----------------------------------------------------------------------
286 * Memory bank 4: USB controller Philips ISP6111
287 * 0x77C00000 ... 0x77CFFFFF
289 * The chip is connected to:
295 * - command to first data: 300ns. Software must ensure this timing!
296 * - Write pulse: 26ns
298 * - read cycle time: 150ns
299 * - write cycle time: 140ns
301 * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
304 * |---- 420ns ---|---- 420ns ---| cycle
305 * CS ############:###____#######:###____#######
306 * OE ############:####___#######:####___#######
307 * WE ############:####__########:####__########
309 * ----> 2 clocks RD/WR pulses: 60ns
310 * ----> CSN: 3 clock, 90ns
311 * ----> OEN: 1 clocks (read cycle)
312 * ----> WBN: 1 clocks (write cycle)
313 * ----> WBE: 2 clocks
314 * ----> TH: 7 clock, 210ns
315 * ----> TWT: 7 clocks
316 *----------------------------------------------------------------------- */
318 #ifdef CONFIG_ISP1161_PRESENT
320 li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
321 mtdcr EBC0_CFGADDR,r4
325 mtdcr EBC0_CFGDATA,r4
327 li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */
328 mtdcr EBC0_CFGADDR,r4
332 mtdcr EBC0_CFGDATA,r4
336 #ifndef IDE_USES_ISA_EMULATION
338 /*-----------------------------------------------------------------------
339 * Memory Bank 5 used for IDE access
341 * Timings for IDE Interface
343 * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
344 * 70 165 30 PIO-Mode 0, [ns]
345 * 3 6 1 [Cycles] ----> AP=0x040C0200
346 * 50 125 20 PIO-Mode 1, [ns]
347 * 2 5 1 [Cycles] ----> AP=0x03080200
348 * 30 100 15 PIO-Mode 2, [ns]
349 * 1 4 1 [Cycles] ----> AP=0x02040200
350 * 30 80 10 PIO-Mode 3, [ns]
351 * 1 3 1 [Cycles] ----> AP=0x01840200
352 * 25 70 10 PIO-Mode 4, [ns]
353 * 1 3 1 [Cycles] ----> AP=0x01840200
355 *----------------------------------------------------------------------- */
358 mtdcr EBC0_CFGADDR,r4
361 mtdcr EBC0_CFGDATA,r4
363 li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */
364 mtdcr EBC0_CFGADDR,r4
368 mtdcr EBC0_CFGDATA,r4
371 * External Peripheral Control Register
374 mtdcr EBC0_CFGADDR,r4
378 mtdcr EBC0_CFGDATA,r4
385 stb r3,0(r4) /* 01 -> external bus controller is initialized */
386 nop /* pass2 DCR errata #8 */