4 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/ic/sc520.h>
30 #include <asm/ic/pci.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 #undef SC520_CDP_DEBUG
39 #ifdef SC520_CDP_DEBUG
40 #define PRINTF(fmt,args...) printf (fmt ,##args)
42 #define PRINTF(fmt,args...)
45 /* ------------------------------------------------------------------------- */
50 * We first set up all IRQs to be non-pci, edge triggered,
51 * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
52 * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
53 * as needed. Whe choose the irqs to gram from a configurable list
54 * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
55 * such as 0 thngas will not work)
58 static void irq_init(void)
60 /* disable global interrupt mode */
61 write_mmcr_byte(SC520_PICICR, 0x40);
63 /* set all irqs to edge */
64 write_mmcr_byte(SC520_MPICMODE, 0x00);
65 write_mmcr_byte(SC520_SL1PICMODE, 0x00);
66 write_mmcr_byte(SC520_SL2PICMODE, 0x00);
68 /* active low polarity on PIC interrupt pins,
69 * active high polarity on all other irq pins */
70 write_mmcr_word(SC520_INTPINPOL, 0x0000);
72 /* set irq number mapping */
73 write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */
74 write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */
75 write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */
76 write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */
77 write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */
78 write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */
79 write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */
80 write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */
81 write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */
82 write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */
83 write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
84 write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED); /* disable Synchronius serial INT */
85 write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */
86 write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */
87 write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */
88 write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */
89 write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */
91 if (CONFIG_SYS_USE_SIO_UART) {
92 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
93 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
94 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
95 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
97 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */
98 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */
99 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ3 (ISA IRQ3) */
100 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ4 (ISA IRQ4) */
103 write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
104 write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
105 write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
106 write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7); /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
107 write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8); /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
108 write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9); /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
109 write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11); /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
110 write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
111 write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14); /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
113 write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */
114 write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */
120 static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
122 /* a configurable lists of irqs to steal
123 * when we need one (a board with more pci interrupt pins
124 * would use a larger table */
125 static int irq_list[] = {
126 CONFIG_SYS_FIRST_PCI_IRQ,
127 CONFIG_SYS_SECOND_PCI_IRQ,
128 CONFIG_SYS_THIRD_PCI_IRQ,
129 CONFIG_SYS_FORTH_PCI_IRQ
131 static int next_irq_index=0;
136 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
139 pin-=1; /* pci config space use 1-based numbering */
141 return; /* device use no irq */
145 /* map device number + pin to a pin on the sc520 */
146 switch (PCI_DEV(dev)) {
167 pin&=3; /* wrap around */
169 if (sc520_pci_ints[pin] == -1) {
170 /* re-route one interrupt for us */
171 if (next_irq_index > 3) {
174 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
181 if (-1 != sc520_pci_ints[pin]) {
182 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
183 sc520_pci_ints[pin]);
185 PRINTF("fixup_irq: device %d pin %c irq %d\n",
186 PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
189 static struct pci_controller sc520_cdp_hose = {
190 fixup_irq: pci_sc520_cdp_fixup_irq,
193 void pci_init_board(void)
195 pci_sc520_init(&sc520_cdp_hose);
199 static void silence_uart(int port)
204 void setup_ali_sio(int uart_primary)
208 ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0);
209 ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3);
210 ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4);
211 ali512x_set_uart(ALI_ENABLED, ALI_UART2, uart_primary?0x2f8:0x2e8, 3);
212 ali512x_set_rtc(ALI_DISABLED, 0, 0);
213 ali512x_set_kbc(ALI_ENABLED, 1, 12);
214 ali512x_set_cio(ALI_ENABLED);
217 ali512x_cio_function(12, 1, 0, 0);
218 ali512x_cio_function(13, 1, 0, 0);
220 /* SSI chip select pins */
221 ali512x_cio_function(14, 0, 0, 0); /* SSI_CS */
222 ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */
223 ali512x_cio_function(16, 0, 0, 0); /* SSI_SPI# */
226 ali512x_cio_function(20, 0, 0, 1);
227 ali512x_cio_function(21, 0, 0, 1);
228 ali512x_cio_function(22, 0, 0, 1);
229 ali512x_cio_function(23, 0, 0, 1);
233 /* set up the ISA bus timing and system address mappings */
234 static void bus_init(void)
237 /* set up the GP IO pins */
238 write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */
239 write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */
240 write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */
241 write_mmcr_byte(SC520_CLKSEL, 0x70);
244 write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */
245 write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */
246 write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */
247 write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */
248 write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */
249 write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */
250 write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */
252 write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */
253 write_mmcr_word(SC520_ROMCS1CTL, 0x1823); /* set up timing of ROMCS1 */
254 write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */
256 /* adjust the memory map:
257 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
258 * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio
259 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
262 /* SRAM = GPCS3 128k @ d0000-effff*/
263 write_mmcr_long(SC520_PAR2, 0x4e00400d);
265 /* IDE0 = GPCS6 1f0-1f7 */
266 write_mmcr_long(SC520_PAR3, 0x380801f0);
268 /* IDE1 = GPCS7 3f6 */
269 write_mmcr_long(SC520_PAR4, 0x3c0003f6);
271 write_mmcr_long(SC520_PAR12, 0x8bffe800);
273 write_mmcr_long(SC520_PAR13, 0xcbfff000);
275 write_mmcr_long(SC520_PAR14, 0xabfff800);
277 write_mmcr_long(SC520_PAR15, 0x30000640);
279 write_mmcr_byte(SC520_ADDDECCTL, 0);
281 asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
283 if (CONFIG_SYS_USE_SIO_UART) {
284 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
287 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
309 * PAR1 PCI ROM mapping
323 * PAR15 Port 0x680 LED display
327 * This function should map a chunk of size bytes
328 * of the system address space to the ISA bus
330 * The function will return the memory address
331 * as seen by the host (which may very will be the
332 * same as the bus address)
334 u32 isa_map_rom(u32 bus_addr, int size)
338 PRINTF("isa_map_rom asked to map %d bytes at %x\n",
349 par |= (bus_addr>>12);
352 PRINTF ("setting PAR11 to %x\n", par);
354 /* Map rom 0x10000 with PAR1 */
355 write_mmcr_long(SC520_PAR11, par);
361 * this function removed any mapping created
362 * with pci_get_rom_window()
364 void isa_unmap_rom(u32 addr)
366 PRINTF("isa_unmap_rom asked to unmap %x", addr);
367 if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
368 write_mmcr_long(SC520_PAR11, 0);
372 PRINTF(" not ours\n");
376 #define PCI_ROM_TEMP_SPACE 0x10000
378 * This function should map a chunk of size bytes
379 * of the system address space to the PCI bus,
380 * suitable to map PCI ROMS (bus address < 16M)
381 * the function will return the host memory address
382 * which should be converted into a bus address
383 * before used to configure the PCI rom address
386 u32 pci_get_rom_window(struct pci_controller *hose, int size)
398 par |= (PCI_ROM_TEMP_SPACE>>16);
401 PRINTF ("setting PAR1 to %x\n", par);
403 /* Map rom 0x10000 with PAR1 */
404 write_mmcr_long(SC520_PAR1, par);
406 return PCI_ROM_TEMP_SPACE;
410 * this function removed any mapping created
411 * with pci_get_rom_window()
413 void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
415 PRINTF("pci_remove_rom_window: %x", addr);
416 if (addr == PCI_ROM_TEMP_SPACE) {
417 write_mmcr_long(SC520_PAR1, 0);
421 PRINTF(" not ours\n");
426 * This function is called in order to provide acces to the
427 * legacy video I/O ports on the PCI bus.
428 * After this function accesses to I/O ports 0x3b0-0x3bb and
429 * 0x3c0-0x3df shuld result in transactions on the PCI bus.
432 int pci_enable_legacy_video_ports(struct pci_controller *hose)
434 /* Map video memory to 0xa0000*/
435 write_mmcr_long(SC520_PAR0, 0x7200400a);
437 /* forward all I/O accesses to PCI */
438 write_mmcr_byte(SC520_ADDDECCTL,
439 read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
442 /* so we map away all io ports to pci (only way to access pci io
443 * below 0x400. But then we have to map back the portions that we dont
444 * use so that the generate cycles on the GPIO bus where the sio and
445 * ISA slots are connected, this requre the use of several PAR registers
448 /* bring 0x100 - 0x1ef back to ISA using PAR5 */
449 write_mmcr_long(SC520_PAR5, 0x30ef0100);
451 /* IDE use 1f0-1f7 */
453 /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
454 write_mmcr_long(SC520_PAR6, 0x30ff01f8);
456 /* com2 use 2f8-2ff */
458 /* bring 0x300 - 0x3af back to ISA using PAR7 */
459 write_mmcr_long(SC520_PAR7, 0x30af0300);
461 /* vga use 3b0-3bb */
463 /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
464 write_mmcr_long(SC520_PAR8, 0x300303bc);
466 /* vga use 3c0-3df */
468 /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
469 write_mmcr_long(SC520_PAR9, 0x301503e0);
473 /* bring 0x3f7 back to ISA using PAR10 */
474 write_mmcr_long(SC520_PAR10, 0x300003f7);
476 /* com1 use 3f8-3ff */
483 * Miscelaneous platform dependent initialisations
492 /* max drive current on SDRAM */
493 write_mmcr_word(SC520_DSCTL, 0x0100);
495 /* enter debug mode after next reset (only if jumper is also set) */
496 write_mmcr_byte(SC520_RESCFG, 0x08);
497 /* configure the software timer to 33.333MHz */
498 write_mmcr_byte(SC520_SWTMRCFG, 0);
499 gd->bus_clk = 33333000;
510 void show_boot_progress(int val)
512 if (val < -32) val = -1; /* let things compatible */
513 outb(val&0xff, 0x80);
514 outb((val&0xff00)>>8, 0x680);
518 int last_stage_init(void)
524 major |= ali512x_cio_in(23)?2:0;
525 major |= ali512x_cio_in(22)?1:0;
526 minor |= ali512x_cio_in(21)?2:0;
527 minor |= ali512x_cio_in(20)?1:0;
529 printf("AMD SC520 CDP revision %d.%d\n", major, minor);
535 void ssi_chip_select(int dev)
538 /* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */
540 case 1: /* SPI EEPROM */
541 ali512x_cio_out(16, 0);
544 case 2: /* MW EEPROM */
545 ali512x_cio_out(15, 1);
549 ali512x_cio_out(14, 1);
553 ali512x_cio_out(16, 1);
554 ali512x_cio_out(15, 0);
555 ali512x_cio_out(14, 0);
559 printf("Illegal SSI device requested: %d\n", dev);
563 void spi_eeprom_probe(int x)
567 int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
572 int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
577 void spi_init_f(void)
579 #ifdef CONFIG_SYS_SC520_CDP_USE_SPI
582 #ifdef CONFIG_SYS_SC520_CDP_USE_MW
587 ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
594 for (i=0;i<alen;i++) {
599 #ifdef CONFIG_SYS_SC520_CDP_USE_SPI
600 res = spi_eeprom_read(1, offset, buffer, len);
602 #ifdef CONFIG_SYS_SC520_CDP_USE_MW
603 res = mw_eeprom_read(2, offset, buffer, len);
605 #if !defined(CONFIG_SYS_SC520_CDP_USE_SPI) && !defined(CONFIG_SYS_SC520_CDP_USE_MW)
611 ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
618 for (i=0;i<alen;i++) {
623 #ifdef CONFIG_SYS_SC520_CDP_USE_SPI
624 res = spi_eeprom_write(1, offset, buffer, len);
626 #ifdef CONFIG_SYS_SC520_CDP_USE_MW
627 res = mw_eeprom_write(2, offset, buffer, len);
629 #if !defined(CONFIG_SYS_SC520_CDP_USE_SPI) && !defined(CONFIG_SYS_SC520_CDP_USE_MW)
635 int board_eth_init(bd_t *bis)
637 return pci_eth_init(bis);