1 // SPDX-License-Identifier: GPL-2.0+
3 * SchulerControl GmbH, SC_SPS_1 module
5 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
6 * on behalf of DENX Software Engineering GmbH
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux-mx28.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <linux/mii.h>
21 DECLARE_GLOBAL_DATA_PTR;
26 int board_early_init_f(void)
28 /* IO0 clock at 480MHz */
29 mxs_set_ioclk(MXC_IOCLK0, 480000);
30 /* IO1 clock at 480MHz */
31 mxs_set_ioclk(MXC_IOCLK1, 480000);
33 /* SSP0 clock at 96MHz */
34 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
35 /* SSP2 clock at 96MHz */
36 mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
39 mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);
40 mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 |
41 MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
42 gpio_direction_output(MX28_PAD_AUART2_TX__GPIO_3_9, 1);
50 /* Adress of boot parameters */
51 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
58 return mxs_dram_init();
62 int board_mmc_init(bd_t *bis)
64 return mxsmmc_initialize(bis, 0, NULL, NULL);
69 int board_eth_init(bd_t *bis)
71 struct mxs_clkctrl_regs *clkctrl_regs =
72 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
75 ret = cpu_eth_init(bis);
77 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
78 CLKCTRL_ENET_TIME_SEL_MASK,
79 CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN);
81 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
83 printf("FEC MXS: Unable to init FEC0\n");
87 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
89 printf("FEC MXS: Unable to init FEC1\n");