2 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
3 * Copyright (C) Sheldon Instruments, Inc. 2008
5 * Author: Ron Madrid <info@sheldoninst.com>
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <spd_sdram.h>
32 #include <asm/bitops.h>
34 #include <asm/processor.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 static long fixed_sdram(void);
41 #if defined(CONFIG_NAND_SPL)
42 void si_wait_i2c(void)
44 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
46 while (!(__raw_readb(&im->i2c[0].sr) & 0x02))
49 __raw_writeb(0x00, &im->i2c[0].sr);
56 void si_read_i2c(u32 lbyte, int count, u8 *buffer)
58 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
60 u8 chip = 0x50 << 1; /* boot sequencer I2C */
61 u32 ubyte = (lbyte & 0xff00) >> 8;
68 __raw_writeb(0x3f, &im->i2c[0].fdr);
69 __raw_writeb(0x00, &im->i2c[0].adr);
70 __raw_writeb(0x00, &im->i2c[0].sr);
71 __raw_writeb(0x00, &im->i2c[0].dr);
73 while (__raw_readb(&im->i2c[0].sr) & 0x20)
77 * Writing address to device
79 __raw_writeb(0xb0, &im->i2c[0].cr);
81 __raw_writeb(chip, &im->i2c[0].dr);
84 __raw_writeb(0xb0, &im->i2c[0].cr);
86 __raw_writeb(ubyte, &im->i2c[0].dr);
89 __raw_writeb(lbyte, &im->i2c[0].dr);
92 __raw_writeb(0xb4, &im->i2c[0].cr);
94 __raw_writeb(chip + 1, &im->i2c[0].dr);
97 __raw_writeb(0xa0, &im->i2c[0].cr);
103 __raw_readb(&im->i2c[0].dr);
110 for (i = 0; i < count; i++)
112 if (i == (count - 2)) /* Reached next to last byte, No ACK */
113 __raw_writeb(0xa8, &im->i2c[0].cr);
114 if (i == (count - 1)) /* Reached last byte, STOP */
115 __raw_writeb(0x88, &im->i2c[0].cr);
117 /* Read byte of data */
118 buffer[i] = __raw_readb(&im->i2c[0].dr);
120 if (i == (count - 1))
127 #endif /* CONFIG_NAND_SPL */
129 phys_size_t initdram(int board_type)
131 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
132 volatile fsl_lbc_t *lbc = &im->im_lbc;
135 if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
138 /* DDR SDRAM - Main SODIMM */
139 __raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);
141 msize = fixed_sdram();
143 /* Local Bus setup lbcr and mrtpr */
144 __raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
145 __raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
148 /* return total bus SDRAM size(bytes) -- DDR */
149 return (msize * 1024 * 1024);
152 /*************************************************************************
153 * fixed sdram init -- reads values from boot sequencer I2C
154 ************************************************************************/
155 static long fixed_sdram(void)
157 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
158 u32 msizelog2, msize = 1;
159 #if defined(CONFIG_NAND_SPL)
161 const u8 bytecount = 135;
162 u8 buffer[bytecount];
165 si_read_i2c(0, bytecount, buffer);
167 for (i = 18; i < bytecount; i += 7){
168 addr = (u32)buffer[i];
170 addr |= (u32)buffer[i + 1];
172 data = (u32)buffer[i + 2];
174 data |= (u32)buffer[i + 3];
176 data |= (u32)buffer[i + 4];
178 data |= (u32)buffer[i + 5];
180 __raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr));
185 /* enable DDR controller */
186 __raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg);
187 #endif /* (CONFIG_NAND_SPL) */
189 msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1);
190 msize <<= (msizelog2 - 20);