2 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
3 * Copyright (C) Sheldon Instruments, Inc. 2008
5 * Author: Ron Madrid <info@sheldoninst.com>
7 * SPDX-License-Identifier: GPL-2.0+
18 DECLARE_GLOBAL_DATA_PTR;
20 #ifndef CONFIG_NAND_SPL
23 puts("Board: Sheldon Instruments SIMPC8313\n");
27 static struct pci_region pci_regions[] = {
29 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
30 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
31 size: CONFIG_SYS_PCI1_MEM_SIZE,
32 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
35 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
36 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
37 size: CONFIG_SYS_PCI1_MMIO_SIZE,
41 bus_start: CONFIG_SYS_PCI1_IO_BASE,
42 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
43 size: CONFIG_SYS_PCI1_IO_SIZE,
48 void pci_init_board(void)
50 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
51 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
52 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
53 struct pci_region *reg[] = { pci_regions };
55 /* Enable all 3 PCI_CLK_OUTPUTs. */
56 clk->occr |= 0xe0000000;
59 * Configure PCI Local Access Windows
61 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
62 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
64 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
65 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
67 mpc83xx_pci_init(1, reg);
71 * Miscellaneous late-boot configurations
76 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
77 fsl_lbc_t *lbus = &immap->im_lbc;
78 u32 *mxmr = &lbus->mamr; /* Pointer to mamr */
80 /* UPM Table Configuration Code */
81 static uint UPMATable[] = {
82 /* Read Single-Beat (RSS) */
83 0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
84 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
85 /* Read Burst (RBS) */
86 0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
87 0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
88 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
89 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
90 /* Write Single-Beat (WSS) */
91 0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
92 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
93 /* Write Burst (WBS) */
94 0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
95 0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
96 0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
97 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
98 /* Refresh Timer (RTS) */
99 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
100 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
101 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
102 /* Exception Condition (EXS) */
103 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
106 upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
108 /* Set LUPWAIT to be active low and enabled */
109 out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
114 #if defined(CONFIG_OF_BOARD_SETUP)
115 void ft_board_setup(void *blob, bd_t *bd)
117 ft_cpu_setup(blob, bd);
119 ft_pci_setup(blob, bd);
123 #else /* CONFIG_NAND_SPL */
124 void board_init_f(ulong bootflag)
126 NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
127 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
128 puts("NAND boot... ");
131 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
132 CONFIG_SYS_NAND_U_BOOT_RELOC);
135 void board_init_r(gd_t *gd, ulong dest_addr)
142 if (gd->flags & GD_FLG_SILENT)
146 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
148 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);