7 #include <linux/stddef.h>
9 #define SYNC __asm__("sync")
10 #define ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))
17 struct atm_connection_t g_conn[NUM_CONNECTIONS] =
19 { NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */
22 struct atm_driver_t g_atm =
30 NULL, /* int_reload_ptr */
31 NULL, /* int_serv_ptr */
32 NULL, /* rbd_base_ptr */
33 NULL, /* tbd_base_ptr */
37 char csram[1024]; /* more than enough for doing nothing*/
42 void atmIntInit(void);
43 void atmApcInit(void);
44 void atmAmtInit(void);
45 void atmCpmInit(void);
46 void atmUtpInit(void);
48 /*****************************************************************************
50 * FUNCTION NAME: atmLoad
52 * DESCRIPTION: Basic ATM initialization.
56 * RETURNS: OK or ERROR
58 ****************************************************************************/
61 volatile immap_t *immap = (immap_t *)CFG_IMMR;
62 volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
63 volatile iop8xx_t *iop = &immap->im_ioport;
65 timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
66 immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
67 iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
69 if ( atmMemInit() != OK ) return ERROR;
82 /*****************************************************************************
84 * FUNCTION NAME: atmUnload
86 * DESCRIPTION: Disables ATM and UTOPIA.
92 ****************************************************************************/
95 volatile immap_t *immap = (immap_t *)CFG_IMMR;
96 volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
97 volatile iop8xx_t *iop = &immap->im_ioport;
99 timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
100 immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
101 iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
102 g_atm.loaded = FALSE;
105 /*****************************************************************************
107 * FUNCTION NAME: atmMemInit
111 * The ATM driver uses the following resources:
113 * A. Memory in DPRAM to hold
115 * 1/ CT = Connection Table ( RCT & TCT )
116 * 2/ TCTE = Transmit Connection Table Extension
117 * 3/ MPHYPT = Multi-PHY Pointing Table
118 * 4/ APCP = APC Parameter Table
119 * 5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 )
120 * 6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR )
121 * 7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR )
122 * 8/ TQ = Transmit Queue
123 * 9/ AM = Address Matching Table
124 * 10/ AP = Address Pointing Table
126 * B. Memory in cache safe RAM to hold
128 * 1/ INT = Interrupt Queue
129 * 2/ RBD = Receive Buffer Descriptors
130 * 3/ TBD = Transmit Buffer Descriptors
133 * 1. clears the ATM DPRAM area,
134 * 2. Allocates and clears cache safe memory,
135 * 3. Initializes 'g_conn'.
139 * RETURNS: OK or ERROR
141 ****************************************************************************/
145 unsigned immr = CFG_IMMR;
146 int total_num_rbd = 0;
147 int total_num_tbd = 0;
149 memset((char *)CFG_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
151 g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY;
153 for ( i = 0; i < NUM_CONNECTIONS; ++i ) {
154 total_num_rbd += g_conn[i].num_rbd;
155 total_num_tbd += g_conn[i].num_tbd;
158 g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4;
160 g_atm.csram = &csram[0];
161 memset(&(g_atm.csram), 0x00, g_atm.csram_size);
163 g_atm.int_reload_ptr = (uint32 *)ALIGN(g_atm.csram, 4);
164 g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES);
165 g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd);
167 g_conn[0].rbd_ptr = g_atm.rbd_base_ptr;
168 g_conn[0].tbd_ptr = g_atm.tbd_base_ptr;
169 g_conn[0].ct_ptr = CT_PTR(immr);
170 g_conn[0].tcte_ptr = TCTE_PTR(immr);
175 /*****************************************************************************
177 * FUNCTION NAME: atmIntInit
181 * Initialization of the MPC860 ESAR Interrupt Queue.
183 * - clears all entries in the INT,
184 * - sets the WRAP bit of the last INT entry,
185 * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure
186 * to the first INT entry.
194 * - The INT resides in external cache safe memory.
195 * - The base address of the INT is stored in g_atm.int_reload_ptr.
196 * - The number of entries in the INT is given by NUM_INT_ENTRIES.
197 * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit().
199 ****************************************************************************/
203 for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0;
204 g_atm.int_reload_ptr[i] = INT_WRAP;
205 g_atm.int_serv_ptr = g_atm.int_reload_ptr;
208 /*****************************************************************************
210 * FUNCTION NAME: atmApcInit
214 * This function initializes the following ATM Pace Controller related
217 * - 1 MPHY Pointing Table (contains only one entry)
218 * - 3 APC Parameter Tables (one PHY with 3 priorities)
219 * - 3 APC Tables (one table for each priority)
220 * - 1 Transmit Queue (one transmit queue per PHY)
226 ****************************************************************************/
230 /* unsigned immr = CFG_IMMR; */
231 uint16 * mphypt_ptr = MPHYPT_PTR(CFG_IMMR);
232 struct apc_params_t * apcp_ptr = APCP_PTR(CFG_IMMR);
233 uint16 * apct_prio1_ptr = APCT1_PTR(CFG_IMMR);
234 uint16 * tq_ptr = TQ_PTR(CFG_IMMR);
235 /***************************************************/
236 /* Initialize MPHY Pointing Table (only one entry) */
237 /***************************************************/
238 *mphypt_ptr = APCP_BASE;
240 /********************************************/
241 /* Initialize APC parameters for priority 1 */
242 /********************************************/
243 apcp_ptr->apct_base1 = APCT_PRIO_1_BASE;
244 apcp_ptr->apct_end1 = APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2;
245 apcp_ptr->apct_ptr1 = APCT_PRIO_1_BASE;
246 apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE;
247 apcp_ptr->etqbase = TQ_BASE;
248 apcp_ptr->etqend = TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2;
249 apcp_ptr->etqaptr = TQ_BASE;
250 apcp_ptr->etqtptr = TQ_BASE;
251 apcp_ptr->apc_mi = 8;
252 apcp_ptr->ncits = 0x0100; /* NCITS = 1 */
254 apcp_ptr->reserved1 = 0;
255 apcp_ptr->eapcst = 0x2009; /* LAST, ESAR, MPHY */
256 apcp_ptr->ptp_counter = 0;
257 apcp_ptr->ptp_txch = 0;
258 apcp_ptr->reserved2 = 0;
261 /***************************************************/
262 /* Initialize APC Tables with empty slots (0xFFFF) */
263 /***************************************************/
264 for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF;
266 /************************/
267 /* Clear Transmit Queue */
268 /************************/
269 for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0;
272 /*****************************************************************************
274 * FUNCTION NAME: atmAmtInit
278 * This function clears the first entry in the Address Matching Table and
279 * lets the first entry in the Address Pointing table point to the first
280 * entry in the TCT table (i.e. the raw cell channel).
288 * The values for the AMBASE, AMEND and APBASE registers in SAR parameter
289 * RAM are initialized by atmCpmInit().
291 ****************************************************************************/
294 unsigned immr = CFG_IMMR;
296 g_atm.am_top = AM_PTR(immr);
297 g_atm.ap_top = AP_PTR(immr);
299 *(g_atm.ap_top--) = CT_BASE;
300 *(g_atm.am_top--) = 0;
303 /*****************************************************************************
305 * FUNCTION NAME: atmCpmInit
309 * This function initializes the Utopia Interface Parameter RAM Map
310 * (SCC4, ATM Protocol) of the Communication Processor Modudule.
316 ****************************************************************************/
319 unsigned immr = CFG_IMMR;
321 memset((char *)immr + 0x3F00, 0x00, 0xC0);
323 /*-----------------------------------------------------------------*/
324 /* RBDBASE - Receive buffer descriptors base address */
325 /* The RBDs reside in cache safe external memory. */
326 /*-----------------------------------------------------------------*/
327 *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr;
329 /*-----------------------------------------------------------------*/
330 /* SRFCR - SAR receive function code */
332 /* 3-4 BO = 11 Byte ordering (big endian). */
333 /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
334 /* when the SDMA channel accesses memory. */
335 /*-----------------------------------------------------------------*/
338 /*-----------------------------------------------------------------*/
339 /* SRSTATE - SAR receive status */
340 /* 0 EXT = 0 Extended mode off. */
341 /* 1 ACP = 0 Valid only if EXT = 1. */
342 /* 2 EC = 0 Standard 53-byte ATM cell. */
343 /* 3 SNC = 0 In sync. Must be set to 0 during initialization. */
344 /* 4 ESAR = 1 Enhanced SAR functionality enabled. */
345 /* 5 MCF = 1 Management Cell Filter active. */
346 /* 6 SER = 0 UTOPIA mode. */
347 /* 7 MPY = 1 Multiple PHY mode. */
348 /*-----------------------------------------------------------------*/
349 *SRSTATE(immr) = 0x0D;
351 /*-----------------------------------------------------------------*/
352 /* MRBLR - Maximum receive buffer length register. */
353 /* Must be cleared for ATM operation (see also SMRBLR). */
354 /*-----------------------------------------------------------------*/
357 /*-----------------------------------------------------------------*/
358 /* RSTATE - SCC internal receive state parameters */
359 /* The first byte must be initialized with the value of SRFCR. */
360 /*-----------------------------------------------------------------*/
361 *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24;
363 /*-----------------------------------------------------------------*/
364 /* STFCR - SAR transmit function code */
366 /* 3-4 BO = 11 Byte ordering (big endian). */
367 /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
368 /* when the SDMA channel accesses memory. */
369 /*-----------------------------------------------------------------*/
372 /*-----------------------------------------------------------------*/
373 /* SRSTATE - SAR transmit status */
374 /* 0 EXT = 0 : Extended mode off */
376 /* 2 EC = 0 : Standard 53-byte ATM cell */
378 /* 4 ESAR = 1 : Enhanced SAR functionality enabled */
380 /* 6 SER = 0 : UTOPIA mode */
381 /* 7 MPY = 1 : Multiple PHY mode */
382 /*-----------------------------------------------------------------*/
383 *STSTATE(immr) = 0x09;
385 /*-----------------------------------------------------------------*/
386 /* TBDBASE - Transmit buffer descriptors base address */
387 /* The TBDs reside in cache safe external memory. */
388 /*-----------------------------------------------------------------*/
389 *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr;
391 /*-----------------------------------------------------------------*/
392 /* TSTATE - SCC internal transmit state parameters */
393 /* The first byte must be initialized with the value of STFCR. */
394 /*-----------------------------------------------------------------*/
395 *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24;
397 /*-----------------------------------------------------------------*/
398 /* CTBASE - Connection table base address */
399 /* Offset from the beginning of DPRAM (64-byte aligned). */
400 /*-----------------------------------------------------------------*/
401 *CTBASE(immr) = CT_BASE;
403 /*-----------------------------------------------------------------*/
404 /* INTBASE - Interrupt queue base pointer. */
405 /* The interrupt queue resides in cache safe external memory. */
406 /*-----------------------------------------------------------------*/
407 *INTBASE(immr) = (uint32)g_atm.int_reload_ptr;
409 /*-----------------------------------------------------------------*/
410 /* INTPTR - Pointer into interrupt queue. */
411 /* Initialize to INTBASE. */
412 /*-----------------------------------------------------------------*/
413 *INTPTR(immr) = *INTBASE(immr);
415 /*-----------------------------------------------------------------*/
416 /* C_MASK - Constant mask for CRC32 */
417 /* Must be initialized to 0xDEBB20E3. */
418 /*-----------------------------------------------------------------*/
419 *C_MASK(immr) = 0xDEBB20E3;
421 /*-----------------------------------------------------------------*/
422 /* INT_ICNT - Interrupt threshold value */
423 /*-----------------------------------------------------------------*/
426 /*-----------------------------------------------------------------*/
427 /* INT_CNT - Interrupt counter */
428 /* Initalize to INT_ICNT. Decremented for each interrupt entry */
429 /* reported in the interrupt queue. On zero an interrupt is */
430 /* signaled to the host by setting the GINT bit in the event */
431 /* register. The counter is reinitialized with INT_ICNT. */
432 /*-----------------------------------------------------------------*/
433 *INT_CNT(immr) = *INT_ICNT(immr);
435 /*-----------------------------------------------------------------*/
436 /* SMRBLR - SAR maximum receive buffer length register. */
437 /* Must be a multiple of 48 bytes. Common for all ATM connections. */
438 /*-----------------------------------------------------------------*/
439 *SMRBLR(immr) = SAR_RXB_SIZE;
441 /*-----------------------------------------------------------------*/
442 /* APCST - APC status register. */
444 /* 1-2 CSER 11 Initialize with the same value as NSER. */
445 /* 3-4 NSER 11 Next serial or UTOPIA channel. */
449 /* 12 ESAR 1 UTOPIA Level 2 MPHY enabled. */
450 /* 13 DIS 0 APC disable. Must be initiazed to 0. */
451 /* 14 PL2 0 Not used. */
452 /* 15 MPY 1 Multiple PHY mode on. */
453 /*-----------------------------------------------------------------*/
454 *APCST(immr) = 0x7809;
456 /*-----------------------------------------------------------------*/
457 /* APCPTR - Pointer to the APC parameter table */
458 /* In MPHY master mode this parameter points to the MPHY pointing */
459 /* table. 2-byte aligned. */
460 /*-----------------------------------------------------------------*/
461 *APCPTR(immr) = MPHYPT_BASE;
463 /*-----------------------------------------------------------------*/
464 /* HMASK - Header mask */
465 /* Each incoming cell is masked with HMASK before being compared */
466 /* to the entries in the address matching table. */
467 /*-----------------------------------------------------------------*/
468 *HMASK(immr) = AM_HMASK;
470 /*-----------------------------------------------------------------*/
471 /* AMBASE - Address matching table base address */
472 /*-----------------------------------------------------------------*/
473 *AMBASE(immr) = AM_BASE;
475 /*-----------------------------------------------------------------*/
476 /* AMEND - Address matching table end address */
477 /*-----------------------------------------------------------------*/
478 *AMEND(immr) = AM_BASE;
480 /*-----------------------------------------------------------------*/
481 /* APBASE - Address pointing table base address */
482 /*-----------------------------------------------------------------*/
483 *APBASE(immr) = AP_BASE;
485 /*-----------------------------------------------------------------*/
486 /* MPHYST - MPHY status register */
488 /* 2-6 NMPHY 00000 1 PHY */
490 /* 10-14 CMPHY 00000 Initialize with same value as NMPHY */
491 /*-----------------------------------------------------------------*/
492 *MPHYST(immr) = 0x0000;
494 /*-----------------------------------------------------------------*/
495 /* TCTEBASE - Transmit connection table extension base address */
496 /* Offset from the beginning of DPRAM (32-byte aligned). */
497 /*-----------------------------------------------------------------*/
498 *TCTEBASE(immr) = TCTE_BASE;
500 /*-----------------------------------------------------------------*/
501 /* Clear not used registers. */
502 /*-----------------------------------------------------------------*/
505 /*****************************************************************************
507 * FUNCTION NAME: atmUtpInit
511 * This function initializes the ATM interface for
516 * - multi PHY (because of a bug in the MPC860P rev. E.0)
517 * - internal clock = SYSCLK / 2
521 * After calling this function, the MPC860ESAR UTOPIA bus is
522 * active and uses the following ports/pins:
524 * Port Pin Signal Description
525 * ------ --- ------- -------------------------------------------
526 * PB[15] R17 TxClav Transmit cell available input/output signal
527 * PC[15] D16 RxClav Receive cell available input/output signal
528 * PD[15] U17 UTPB[0] UTOPIA bus bit 0 input/output signal
529 * PD[14] V19 UTPB[1] UTOPIA bus bit 1 input/output signal
530 * PD[13] V18 UTPB[2] UTOPIA bus bit 2 input/output signal
531 * PD[12] R16 UTPB[3] UTOPIA bus bit 3 input/output signal
532 * PD[11] T16 RXENB Receive enable input/output signal
533 * PD[10] W18 TXENB Transmit enable input/output signal
534 * PD[9] V17 UTPCLK UTOPIA clock input/output signal
535 * PD[7] T15 UTPB[4] UTOPIA bus bit 4 input/output signal
536 * PD[6] V16 UTPB[5] UTOPIA bus bit 5 input/output signal
537 * PD[5] U15 UTPB[6] UTOPIA bus bit 6 input/output signal
538 * PD[4] U16 UTPB[7] UTOPIA bus bit 7 input/output signal
539 * PD[3] W16 SOC Start of cell input/output signal
547 * The ATM parameters and data structures must be configured before
548 * initializing the UTOPIA port. The UTOPIA port activates immediately
549 * upon initialization, and if its associated data structures are not
550 * initialized, the CPM will lock up.
552 ****************************************************************************/
555 volatile immap_t *immap = (immap_t *)CFG_IMMR;
556 volatile iop8xx_t *iop = &immap->im_ioport;
557 volatile car8xx_t *car = &immap->im_clkrst;
558 volatile cpm8xx_t *cpm = &immap->im_cpm;
561 flag = disable_interrupts();
563 /*-----------------------------------------------------------------*/
564 /* SCCR - System Clock Control Register */
566 /* The UTOPIA clock can be selected to be internal clock or */
567 /* external clock (selected by the UTOPIA mode register). */
568 /* In case of internal clock, the UTOPIA clock is derived from */
569 /* the system frequency divided by two dividers. */
570 /* Bits 27-31 of the SCCR register are defined to control the */
573 /* SCCR[27:29] DFUTP Division factor. Divide the system clock */
575 /* SCCR[30:31] DFAUTP Additional division factor. Divide the */
576 /* system clock by the following value: */
577 /* 00 = divide by 1 */
578 /* 00 = divide by 3 */
579 /* 10 = divide by 5 */
580 /* 11 = divide by 7 */
582 /* Note that the UTOPIA clock must be programmed as to operate */
583 /* within the range SYSCLK/10 .. 50Mhz. */
584 /*-----------------------------------------------------------------*/
585 car->car_sccr &= 0xFFFFFFE0;
586 car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */
588 /*-----------------------------------------------------------------*/
589 /* RCCR - RISC Controller Configuration Register */
591 /* RCCR[8] DR1M IDMA Request 0 Mode */
592 /* 0 = edge sensitive */
593 /* 1 = level sensitive */
594 /* RCCR[9] DR0M IDMA Request 0 Mode */
595 /* 0 = edge sensitive */
596 /* 1 = level sensitive */
597 /* RCCR[10:11] DRQP IDMA Request Priority */
598 /* 00 = IDMA req. have more prio. than SCCs */
599 /* 01 = IDMA req. have less prio. then SCCs */
600 /* 10 = IDMA requests have the lowest prio. */
603 /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */
604 /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */
605 /* higher priority. */
606 /*-----------------------------------------------------------------*/
607 cpm->cp_rccr &= 0xFF0F;
608 cpm->cp_rccr |= 0x00D0;
610 /*-----------------------------------------------------------------*/
611 /* Port B - TxClav Signal */
612 /*-----------------------------------------------------------------*/
613 cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */
614 cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */
616 /*-----------------------------------------------------------------*/
617 /* UTOPIA Mode Register */
619 /* - muxed bus (master operation only) */
620 /* - multi PHY (because of a bug in the MPC860P rev.E.0) */
621 /* - internal clock */
623 /* - do no activate statistical counters */
624 /*-----------------------------------------------------------------*/
625 iop->utmode = 0x00000004; SYNC;
627 /*-----------------------------------------------------------------*/
628 /* Port D - UTOPIA Data and Control Signals */
630 /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals */
631 /* 11 RXENB UTOPIA receive enable input/output signal */
632 /* 10 TXENB UTOPIA transmit enable input/output signal */
633 /* 9 TUPCLK UTOPIA clock input/output signal */
634 /* 8 MII-MDC Used by MII in simult. MII and UTOPIA operation */
635 /* 7-4 UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals */
636 /* 3 SOC UTOPIA Start of cell input/output signal */
638 /* 1 Enable UTOPIA mode */
640 /*-----------------------------------------------------------------*/
641 iop->iop_pdpar |= 0xDF7F; SYNC;
642 iop->iop_pddir &= 0x2080; SYNC;
644 /*-----------------------------------------------------------------*/
645 /* Port C - RxClav Signal */
646 /*-----------------------------------------------------------------*/
647 iop->iop_pcpar |= 0x0001; /* PCPAR[15] = 1 */
648 iop->iop_pcdir &= 0xFFFE; /* PCDIR[15] = 0 */
649 iop->iop_pcso &= 0xFFFE; /* PCSO[15] = 0 */