3 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <linux/ctype.h>
32 int power_on_reset(void);
34 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
37 static int fpga_get_version(fpga_t* fpga, char* name)
41 * Net-list string format:
42 * "vvvvvvvvddddddddn...".
44 * "0000000322042002PUMA" = PUMA version 3 from 22.04.2002.
46 if (strlen(name) < (16 + strlen(fpga->name)))
49 if (strcmp(&name[16], fpga->name) != 0)
51 /* Get version number */
52 memcpy(vname, name, 8);
54 return simple_strtoul(vname, NULL, 16);
57 printf("Image name %s is invalid\n", name);
61 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
63 static fpga_t* fpga_get(char* fpga_name)
65 char name[FPGA_NAME_LEN];
68 if (strlen(fpga_name) >= FPGA_NAME_LEN)
70 for (i = 0; i < strlen(fpga_name); i++)
71 name[i] = toupper(fpga_name[i]);
73 for (i = 0; i < fpga_count; i++) {
74 if (strcmp(name, fpga_list[i].name) == 0)
78 printf("FPGA: name %s is invalid\n", fpga_name);
82 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
84 static void fpga_status (fpga_t* fpga)
87 if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
88 printf ("%s is loaded (%08lx)\n",
89 fpga->name, fpga_control(fpga, FPGA_GET_ID));
91 printf ("%s is NOT loaded\n", fpga->name);
94 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
96 #define FPGA_RESET_TIMEOUT 100 /* = 10 ms */
98 static int fpga_reset (fpga_t* fpga)
102 /* Set PROG to low and wait til INIT goes low */
103 fpga_control(fpga, FPGA_PROG_SET_LOW);
104 for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
106 if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
109 if (i == FPGA_RESET_TIMEOUT)
112 /* Set PROG to high and wait til INIT goes high */
113 fpga_control(fpga, FPGA_PROG_SET_HIGH);
114 for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
116 if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
119 if (i == FPGA_RESET_TIMEOUT)
127 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
129 #define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
131 static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
133 volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
134 image_header_t *hdr = (image_header_t *)addr;
141 * Check the image header and data of the net-list
143 if (!image_check_magic (hdr)) {
144 strcpy (msg, "Bad Image Magic Number");
148 if (!image_check_hcrc (hdr)) {
149 strcpy (msg, "Bad Image Header CRC");
153 data = (uchar*)image_get_data (hdr);
154 len = image_get_data_size (hdr);
156 verify = getenv_verify ();
158 if (!image_check_dcrc (hdr)) {
159 strcpy (msg, "Bad Image Data CRC");
164 if (checkall && fpga_get_version(fpga, image_get_name (hdr)) < 0)
172 * Reset FPGA and wait for completion
174 if (fpga_reset(fpga)) {
175 strcpy (msg, "Reset Timeout");
179 printf ("(%s)... ", image_get_name (hdr));
183 fpga_control (fpga, FPGA_LOAD_MODE);
185 *fpga_addr = *data++;
187 fpga_control (fpga, FPGA_READ_MODE);
190 * Wait for completion and check error status if timeout
192 for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
194 if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
197 if (i == FPGA_LOAD_TIMEOUT) {
198 if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
199 strcpy(msg, "Invalid Size");
201 strcpy(msg, "CRC Error");
210 printf("ERROR: %s\n", msg);
214 #if defined(CONFIG_CMD_BSP)
216 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
218 int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
227 if (strncmp(argv[1], "stat", 4) == 0) { /* status */
229 for (i = 0; i < fpga_count; i++) {
230 fpga_status (&fpga_list[i]);
233 else if (argc == 3) {
234 if ((fpga = fpga_get(argv[2])) == 0)
241 else if (strcmp(argv[1],"load") == 0) { /* load */
242 if (argc == 3 && fpga_count == 1) {
243 fpga = &fpga_list[0];
245 else if (argc == 4) {
246 if ((fpga = fpga_get(argv[2])) == 0)
252 addr = simple_strtoul(argv[argc-1], NULL, 16);
254 printf ("FPGA load %s: addr %08lx: ",
256 fpga_load (fpga, addr, 1);
259 else if (strncmp(argv[1], "rese", 4) == 0) { /* reset */
260 if (argc == 2 && fpga_count == 1) {
261 fpga = &fpga_list[0];
263 else if (argc == 3) {
264 if ((fpga = fpga_get(argv[2])) == 0)
270 printf ("FPGA reset %s: ", fpga->name);
271 if (fpga_reset(fpga))
272 printf ("ERROR: Timeout\n");
282 printf ("Usage:\n%s\n", cmdtp->usage);
288 "fpga - access FPGA(s)\n",
289 "fpga status [name] - print FPGA status\n"
290 "fpga reset [name] - reset FPGA\n"
291 "fpga load [name] addr - load FPGA configuration data\n"
296 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
301 ulong new_id, old_id = 0;
308 * Port setup for FPGA control
310 for (i = 0; i < fpga_count; i++) {
311 fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
315 * Load FPGA(s): a new net-list is loaded if the FPGA is
316 * empty, Power-on-Reset or the old one is not up-to-date
318 for (i = 0; i < fpga_count; i++) {
319 fpga = &fpga_list[i];
320 printf ("%s: ", fpga->name);
322 for (j = 0; j < strlen(fpga->name); j++)
323 name[j] = tolower(fpga->name[j]);
325 sprintf(name, "%s_addr", name);
327 if ((s = getenv(name)) != NULL)
328 addr = simple_strtoul(s, NULL, 16);
331 printf ("env. variable %s undefined\n", name);
335 hdr = (image_header_t *)addr;
336 if ((new_id = fpga_get_version(fpga, image_get_name (hdr))) == -1)
341 if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
342 old_id = fpga_control(fpga, FPGA_GET_ID);
343 if (new_id == old_id)
349 fpga_load (fpga, addr, 0);
351 printf ("loaded (%08lx)\n", old_id);