3 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <linux/ctype.h>
34 int power_on_reset(void);
36 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
39 static int fpga_get_version(fpga_t* fpga, char* name)
43 * Net-list string format:
44 * "vvvvvvvvddddddddn...".
46 * "0000000322042002PUMA" = PUMA version 3 from 22.04.2002.
48 if (strlen(name) < (16 + strlen(fpga->name)))
51 if (strcmp(&name[16], fpga->name) != 0)
53 /* Get version number */
54 memcpy(vname, name, 8);
56 return simple_strtoul(vname, NULL, 16);
59 printf("Image name %s is invalid\n", name);
63 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
65 static fpga_t* fpga_get(char* fpga_name)
67 char name[FPGA_NAME_LEN];
70 if (strlen(fpga_name) >= FPGA_NAME_LEN)
72 for (i = 0; i < strlen(fpga_name); i++)
73 name[i] = toupper(fpga_name[i]);
75 for (i = 0; i < fpga_count; i++) {
76 if (strcmp(name, fpga_list[i].name) == 0)
80 printf("FPGA: name %s is invalid\n", fpga_name);
84 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
86 static void fpga_status (fpga_t* fpga)
89 if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
90 printf ("%s is loaded (%08lx)\n",
91 fpga->name, fpga_control(fpga, FPGA_GET_ID));
93 printf ("%s is NOT loaded\n", fpga->name);
96 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
98 #define FPGA_RESET_TIMEOUT 100 /* = 10 ms */
100 static int fpga_reset (fpga_t* fpga)
104 /* Set PROG to low and wait til INIT goes low */
105 fpga_control(fpga, FPGA_PROG_SET_LOW);
106 for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
108 if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
111 if (i == FPGA_RESET_TIMEOUT)
114 /* Set PROG to high and wait til INIT goes high */
115 fpga_control(fpga, FPGA_PROG_SET_HIGH);
116 for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
118 if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
121 if (i == FPGA_RESET_TIMEOUT)
129 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
131 #define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
133 static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
135 volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
138 uchar *data = (uchar *)&hdr;
143 * Check the image header and data of the net-list
145 memcpy (&hdr, (char *)addr, sizeof(image_header_t));
147 if (hdr.ih_magic != IH_MAGIC) {
148 strcpy (msg, "Bad Image Magic Number");
152 len = sizeof(image_header_t);
154 checksum = hdr.ih_hcrc;
157 if (crc32 (0, data, len) != checksum) {
158 strcpy (msg, "Bad Image Header CRC");
162 data = (uchar*)(addr + sizeof(image_header_t));
165 s = getenv ("verify");
166 verify = (s && (*s == 'n')) ? 0 : 1;
168 if (crc32 (0, data, len) != hdr.ih_dcrc) {
169 strcpy (msg, "Bad Image Data CRC");
174 if (checkall && fpga_get_version(fpga, hdr.ih_name) < 0)
182 * Reset FPGA and wait for completion
184 if (fpga_reset(fpga)) {
185 strcpy (msg, "Reset Timeout");
189 printf ("(%s)... ", hdr.ih_name);
193 fpga_control (fpga, FPGA_LOAD_MODE);
195 *fpga_addr = *data++;
197 fpga_control (fpga, FPGA_READ_MODE);
200 * Wait for completion and check error status if timeout
202 for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
204 if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
207 if (i == FPGA_LOAD_TIMEOUT) {
208 if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
209 strcpy(msg, "Invalid Size");
211 strcpy(msg, "CRC Error");
220 printf("ERROR: %s\n", msg);
224 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
226 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
228 int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
237 if (strncmp(argv[1], "stat", 4) == 0) { /* status */
239 for (i = 0; i < fpga_count; i++) {
240 fpga_status (&fpga_list[i]);
243 else if (argc == 3) {
244 if ((fpga = fpga_get(argv[2])) == 0)
251 else if (strcmp(argv[1],"load") == 0) { /* load */
252 if (argc == 3 && fpga_count == 1) {
253 fpga = &fpga_list[0];
255 else if (argc == 4) {
256 if ((fpga = fpga_get(argv[2])) == 0)
262 addr = simple_strtoul(argv[argc-1], NULL, 16);
264 printf ("FPGA load %s: addr %08lx: ",
266 fpga_load (fpga, addr, 1);
269 else if (strncmp(argv[1], "rese", 4) == 0) { /* reset */
270 if (argc == 2 && fpga_count == 1) {
271 fpga = &fpga_list[0];
273 else if (argc == 3) {
274 if ((fpga = fpga_get(argv[2])) == 0)
280 printf ("FPGA reset %s: ", fpga->name);
281 if (fpga_reset(fpga))
282 printf ("ERROR: Timeout\n");
292 printf ("Usage:\n%s\n", cmdtp->usage);
296 #endif /* CONFIG_COMMANDS & CFG_CMD_BSP */
298 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
303 ulong new_id, old_id = 0;
310 * Port setup for FPGA control
312 for (i = 0; i < fpga_count; i++) {
313 fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
317 * Load FPGA(s): a new net-list is loaded if the FPGA is
318 * empty, Power-on-Reset or the old one is not up-to-date
320 for (i = 0; i < fpga_count; i++) {
321 fpga = &fpga_list[i];
322 printf ("%s: ", fpga->name);
324 for (j = 0; j < strlen(fpga->name); j++)
325 name[j] = tolower(fpga->name[j]);
327 sprintf(name, "%s_addr", name);
329 if ((s = getenv(name)) != NULL)
330 addr = simple_strtoul(s, NULL, 16);
333 printf ("env. variable %s undefined\n", name);
337 hdr = (image_header_t *)addr;
338 if ((new_id = fpga_get_version(fpga, hdr->ih_name)) == -1)
343 if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
344 old_id = fpga_control(fpga, FPGA_GET_ID);
345 if (new_id == old_id)
351 fpga_load (fpga, addr, 0);
353 printf ("loaded (%08lx)\n", old_id);