2 * Board functions for TI AM335X based rut board
3 * (C) Copyright 2013 Siemens Schweiz AG
4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * u-boot:/board/ti/am335x/board.c
9 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
11 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/omap.h>
21 #include <asm/arch/ddr_defs.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/sys_proto.h>
35 #include "../common/factoryset.h"
36 #include "../../../drivers/video/da8xx-fb.h"
38 DECLARE_GLOBAL_DATA_PTR;
41 * Read header information from EEPROM into global structure.
43 static int read_eeprom(void)
48 #ifdef CONFIG_SPL_BUILD
49 static void board_init_ddr(void)
51 struct emif_regs rut_ddr3_emif_reg_data = {
52 .sdram_config = 0x61C04AB2,
53 .sdram_tim1 = 0x0888A39B,
54 .sdram_tim2 = 0x26337FDA,
55 .sdram_tim3 = 0x501F830F,
56 .emif_ddr_phy_ctlr_1 = 0x6,
57 .zq_config = 0x50074BE4,
61 struct ddr_data rut_ddr3_data = {
62 .datardsratio0 = 0x3b,
63 .datawdsratio0 = 0x85,
64 .datafwsratio0 = 0x100,
65 .datawrsratio0 = 0xc1,
68 struct cmd_control rut_ddr3_cmd_ctrl_data = {
77 config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
78 &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
81 static int request_and_pulse_reset(int gpio, const char *name)
84 const int delay_us = 2000; /* 2ms */
86 ret = gpio_request(gpio, name);
88 printf("%s: Unable to request %s\n", __func__, name);
92 ret = gpio_direction_output(gpio, 0);
94 printf("%s: Unable to set %s as output\n", __func__, name);
100 gpio_set_value(gpio, 1);
110 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
111 #define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
112 #define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
113 #define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
115 #define REQUEST_AND_PULSE_RESET(N) \
116 request_and_pulse_reset(N, #N);
118 static void spl_siemens_board_init(void)
120 REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
121 REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
122 REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
124 #endif /* if def CONFIG_SPL_BUILD */
126 #if defined(CONFIG_DRIVER_TI_CPSW)
127 static void cpsw_control(int enabled)
129 /* VTP can be added here */
134 static struct cpsw_slave_data cpsw_slaves[] = {
136 .slave_reg_ofs = 0x208,
137 .sliver_reg_ofs = 0xd80,
139 .phy_if = PHY_INTERFACE_MODE_RMII,
142 .slave_reg_ofs = 0x308,
143 .sliver_reg_ofs = 0xdc0,
145 .phy_if = PHY_INTERFACE_MODE_RMII,
149 static struct cpsw_platform_data cpsw_data = {
150 .mdio_base = CPSW_MDIO_BASE,
151 .cpsw_base = CPSW_BASE,
154 .cpdma_reg_ofs = 0x800,
156 .slave_data = cpsw_slaves,
157 .ale_reg_ofs = 0xd00,
159 .host_port_reg_ofs = 0x108,
160 .hw_stats_reg_ofs = 0x900,
161 .bd_ram_ofs = 0x2000,
162 .mac_control = (1 << 5),
163 .control = cpsw_control,
165 .version = CPSW_CTRL_VERSION_2,
168 #if defined(CONFIG_DRIVER_TI_CPSW) || \
169 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
170 int board_eth_init(bd_t *bis)
172 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
176 #ifndef CONFIG_SPL_BUILD
180 /* Set rgmii mode and enable rmii clock to be sourced from chip */
181 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
183 rv = cpsw_register(&cpsw_data);
185 printf("Error %d registering CPSW switch\n", rv);
190 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
191 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
193 #if defined(CONFIG_HW_WATCHDOG)
194 static bool hw_watchdog_init_done;
195 static int hw_watchdog_trigger_level;
197 void hw_watchdog_reset(void)
199 if (!hw_watchdog_init_done)
202 hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
203 gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
206 void hw_watchdog_init(void)
208 gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
209 gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
213 hw_watchdog_init_done = 1;
215 #endif /* defined(CONFIG_HW_WATCHDOG) */
217 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
218 static struct da8xx_panel lcd_panels[] = {
219 /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
221 .name = "KWH043MC17-F01",
224 .hfp = 50, /* no spec, "don't care" values */
230 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
233 /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
235 .name = "KWH043ST20-F01",
238 .hfp = 50, /* no spec, "don't care" values */
244 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
247 /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
249 .name = "MI0430VT-1",
252 .hfp = 50, /* no spec, "don't care" values */
258 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
263 static const struct display_panel disp_panels[] = {
284 static const struct lcd_ctrl_config lcd_cfgs[] = {
295 .invert_line_clock = 1,
296 .invert_frm_clock = 1,
311 .invert_line_clock = 1,
312 .invert_frm_clock = 1,
327 .invert_line_clock = 1,
328 .invert_frm_clock = 1,
336 /* no console on this board */
337 int board_cfb_skip(void)
342 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
343 #define PLL_GET_N(v) (v & 0x7f)
345 static struct dpll_regs dpll_lcd_regs = {
346 .cm_clkmode_dpll = CM_WKUP + 0x98,
347 .cm_idlest_dpll = CM_WKUP + 0x48,
348 .cm_clksel_dpll = CM_WKUP + 0x54,
351 static int get_clk(struct dpll_regs *dpll_regs)
357 val = readl(dpll_regs->cm_clksel_dpll);
360 f = (m * V_OSCK) / n;
367 return get_clk(&dpll_lcd_regs);
370 static int conf_disp_pll(int m, int n)
372 struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
373 struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
374 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
375 struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
378 u32 *const clk_domains[] = {
382 u32 *const clk_modules_explicit_en[] = {
384 &cmper->lcdcclkstctrl,
388 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
390 do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
392 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
393 writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
394 writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
395 writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12),
396 &cmwkup->clkmoddplldisp); /* 0x98 */
401 static int set_gpio(int gpio, int state)
403 gpio_request(gpio, "temp");
404 gpio_direction_output(gpio, state);
405 gpio_set_value(gpio, state);
410 static int enable_lcd(void)
412 unsigned char buf[1];
414 set_gpio(BOARD_LCD_RESET, 0);
416 set_gpio(BOARD_LCD_RESET, 1);
420 kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
424 i2c_write(0x24, 0x7, 1, buf, 1);
426 i2c_write(0x24, 0x8, 1, buf, 1);
430 int arch_early_init_r(void)
436 static int board_video_init(void)
439 int anzdisp = ARRAY_SIZE(lcd_panels);
442 for (i = 0; i < anzdisp; i++) {
443 if (strncmp((const char *)factory_dat.disp_name,
445 strlen((const char *)factory_dat.disp_name)) == 0) {
446 printf("DISPLAY: %s\n", factory_dat.disp_name);
452 printf("%s: %s not found, using default %s\n", __func__,
453 factory_dat.disp_name, lcd_panels[i].name);
455 conf_disp_pll(24, 1);
456 da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
457 lcd_cfgs[display].bpp);
461 #endif /* ifdef CONFIG_VIDEO */
462 #include "../common/board.c"