6 * Simple Network Magic Corporation, dnevil@snmc.com
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/u-boot.h>
19 /* ------------------------------------------------------------------------- */
21 static long int dram_size (long int, long int *, long int);
23 /* ------------------------------------------------------------------------- */
25 const uint sdram_table[] =
28 * Single Read. (Offset 0 in UPMA RAM)
30 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
31 0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35,
33 * Burst Read. (Offset 8 in UPMA RAM)
35 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
36 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,
37 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
38 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
40 * Single Write. (Offset 18 in UPMA RAM)
42 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,
43 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
45 * Burst Write. (Offset 20 in UPMA RAM)
47 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
48 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04,
49 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
50 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
52 * Refresh (Offset 30 in UPMA RAM)
54 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
55 0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04,
56 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
58 * Exception. (Offset 3c in UPMA RAM)
60 0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04
63 /* ------------------------------------------------------------------------- */
67 * Check Board Identity:
69 * Test ID string (QS860T...)
80 i = getenv_f("serial#", buf, sizeof(buf));
81 s = (i>0) ? buf : NULL;
83 if (!s || strncmp(s, "QS860T", 6)) {
84 puts ("### No HW ID - assuming QS860T");
100 /* ------------------------------------------------------------------------- */
102 phys_size_t initdram (int board_type)
104 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
105 volatile memctl8xx_t *memctl = &immap->im_memctl;
108 upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
111 * Prescaler for refresh
113 memctl->memc_mptpr = 0x0400;
116 * Map controller bank 2 to the SDRAM address
118 memctl->memc_or2 = CONFIG_SYS_OR2;
119 memctl->memc_br2 = CONFIG_SYS_BR2;
122 /* perform SDRAM initialization sequence */
123 memctl->memc_mbmr = CONFIG_SYS_16M_MBMR;
126 memctl->memc_mar = 0x00000088;
127 memctl->memc_mcr = 0x80804105; /* run precharge pattern */
130 /* Run two refresh cycles on SDRAM */
131 memctl->memc_mbmr = 0x18802118;
132 memctl->memc_mcr = 0x80804130;
133 memctl->memc_mbmr = 0x18802114;
134 memctl->memc_mcr = 0x80804106;
140 * Check for 64M SDRAM Memory Size
142 size = dram_size (CONFIG_SYS_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE);
146 * Check for 16M SDRAM Memory Size
148 if (size != SDRAM_64M_MAX_SIZE) {
150 size = dram_size (CONFIG_SYS_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
155 memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
165 * Also, map other memory to correct position
169 * Map the 8M Intel Flash device to chip select 1
171 memctl->memc_or1 = CONFIG_SYS_OR1;
172 memctl->memc_br1 = CONFIG_SYS_BR1;
176 * Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg
179 memctl->memc_or3 = CONFIG_SYS_OR3;
180 memctl->memc_br3 = CONFIG_SYS_BR3;
183 * Map chip selects 4, 5, 6, & 7 for external expansion connector
185 memctl->memc_or4 = CONFIG_SYS_OR4;
186 memctl->memc_br4 = CONFIG_SYS_BR4;
188 memctl->memc_or5 = CONFIG_SYS_OR5;
189 memctl->memc_br5 = CONFIG_SYS_BR5;
191 memctl->memc_or6 = CONFIG_SYS_OR6;
192 memctl->memc_br6 = CONFIG_SYS_BR6;
194 memctl->memc_or7 = CONFIG_SYS_OR7;
195 memctl->memc_br7 = CONFIG_SYS_BR7;
202 /* ------------------------------------------------------------------------- */
205 * Check memory range for valid RAM. A simple memory test determines
206 * the actually available RAM size between addresses `base' and
207 * `base + maxsize'. Some (not all) hardware errors are detected:
208 * - short between address lines
209 * - short between data lines
212 static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
214 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
215 volatile memctl8xx_t *memctl = &immap->im_memctl;
217 memctl->memc_mbmr = mbmr_value;
219 return (get_ram_size(base, maxsize));