3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5 * Copyright 2004 Freescale Semiconductor.
6 * (C) Copyright 2002,2003, Motorola Inc.
7 * Xianghua Xiao, (X.Xiao@motorola.com)
9 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/processor.h>
17 #include <asm/immap_85xx.h>
21 #include <fdt_support.h>
26 #include "upm_table.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 extern flash_info_t flash_info[]; /* FLASH chips info */
31 extern GraphicDevice mb862xx;
33 void local_bus_init (void);
34 ulong flash_get_size (ulong base, int banknum);
38 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
41 int i = getenv_f("serial#", buf, sizeof(buf));
46 puts("Board: Socrates");
54 /* Check the PCI_clk sel bit */
55 if (in_be32(&gur->porpllsr) & (1<<15)) {
57 f = CONFIG_SYS_CLK_FREQ;
60 f = CONFIG_PCI_CLK_FREQ;
62 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
64 printf ("PCI1: disabled\n");
68 * Initialize local bus.
74 int misc_init_r (void)
77 * Adjust flash start and offset to detected values
79 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
80 gd->bd->bi_flashoffset = 0;
83 * Check if boot FLASH isn't max size
85 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
86 set_lbc_or(0, gd->bd->bi_flashstart |
87 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
88 set_lbc_br(0, gd->bd->bi_flashstart |
89 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
92 * Re-check to get correct base address
94 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
98 * Check if only one FLASH bank is available
100 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
105 * Re-do flash protection upon new addresses
107 flash_protect (FLAG_PROTECT_CLEAR,
108 gd->bd->bi_flashstart, 0xffffffff,
109 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
111 /* Monitor protection ON by default */
112 flash_protect (FLAG_PROTECT_SET,
113 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
114 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
116 /* Environment protection ON by default */
117 flash_protect (FLAG_PROTECT_SET,
119 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
120 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
122 /* Redundant environment protection ON by default */
123 flash_protect (FLAG_PROTECT_SET,
124 CONFIG_ENV_ADDR_REDUND,
125 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
126 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
133 * Initialize Local Bus
135 void local_bus_init (void)
137 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
138 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
142 uint lcrr = CONFIG_SYS_LBC_LCRR;
144 get_sys_info (&sysinfo);
145 clkdiv = lbc->lcrr & LCRR_CLKDIV;
146 lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
148 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
150 lcrr &= ~LCRR_DBYP; /* DLL Enabled */
152 lcrr |= LCRR_DBYP; /* DLL Bypass */
154 out_be32 (&lbc->lcrr, lcrr);
155 asm ("sync;isync;msync");
157 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
158 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
159 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
160 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
162 /* Init UPMA for FPGA access */
163 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
164 upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
166 /* Init UPMB for Lime controller access */
167 out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
168 upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
171 #if defined(CONFIG_PCI)
173 * Initialize PCI Devices, report devices found.
176 #ifndef CONFIG_PCI_PNP
177 static struct pci_config_table pci_mpc85xxads_config_table[] = {
178 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
179 PCI_IDSEL_NUMBER, PCI_ANY_ID,
180 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
183 PCI_COMMAND_MASTER}},
189 static struct pci_controller hose = {
190 #ifndef CONFIG_PCI_PNP
191 config_table:pci_mpc85xxads_config_table,
195 #endif /* CONFIG_PCI */
198 void pci_init_board (void)
201 pci_mpc85xx_init (&hose);
202 #endif /* CONFIG_PCI */
205 #ifdef CONFIG_BOARD_EARLY_INIT_R
206 int board_early_init_r (void)
208 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
210 /* set and reset the GPIO pin 2 which will reset the W83782G chip */
211 out_8((unsigned char*)&gur->gpoutdr, 0x3F );
212 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
214 out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
218 #endif /* CONFIG_BOARD_EARLY_INIT_R */
220 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
221 int ft_board_setup(void *blob, bd_t *bd)
226 ft_cpu_setup(blob, bd);
228 /* Fixup NOR FLASH mapping */
229 val[i++] = 0; /* chip select number */
230 val[i++] = 0; /* always 0 */
231 val[i++] = gd->bd->bi_flashstart;
232 val[i++] = gd->bd->bi_flashsize;
234 if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
235 /* Fixup LIME mapping */
236 val[i++] = 2; /* chip select number */
237 val[i++] = 0; /* always 0 */
238 val[i++] = CONFIG_SYS_LIME_BASE;
239 val[i++] = CONFIG_SYS_LIME_SIZE;
242 /* Fixup FPGA mapping */
243 val[i++] = 3; /* chip select number */
244 val[i++] = 0; /* always 0 */
245 val[i++] = CONFIG_SYS_FPGA_BASE;
246 val[i++] = CONFIG_SYS_FPGA_SIZE;
248 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
249 val, i * sizeof(u32), 1);
251 printf("Unable to update localbus ranges, err=%s\n",
256 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
258 #define DEFAULT_BRIGHTNESS 25
259 #define BACKLIGHT_ENABLE (1 << 31)
261 static const gdc_regs init_regs [] =
263 {0x0100, 0x00010f00},
264 {0x0020, 0x801901df},
265 {0x0024, 0x00000000},
266 {0x0028, 0x00000000},
267 {0x002c, 0x00000000},
268 {0x0110, 0x00000000},
269 {0x0114, 0x00000000},
270 {0x0118, 0x01df0320},
271 {0x0004, 0x041f0000},
272 {0x0008, 0x031f031f},
273 {0x000c, 0x017f0349},
274 {0x0010, 0x020c0000},
275 {0x0014, 0x01df01e9},
276 {0x0018, 0x00000000},
277 {0x001c, 0x01e00320},
278 {0x0100, 0x80010f00},
282 const gdc_regs *board_get_regs (void)
293 cfg_br2 = get_lbc_br(2);
294 cfg_or2 = get_lbc_or(2);
296 /* Configure GPCM for CS2 */
298 set_lbc_or(2, 0xfc000410);
299 set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
301 /* Get controller type */
302 type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
304 /* Restore previous CS2 configuration */
306 set_lbc_or(2, cfg_or2);
307 set_lbc_br(2, cfg_br2);
309 return (type == MB862XX_TYPE_LIME) ? 1 : 0;
312 /* Returns Lime base address */
313 unsigned int board_video_init (void)
318 mb862xx.winSizeX = 800;
319 mb862xx.winSizeY = 480;
320 mb862xx.gdfIndex = GDF_15BIT_555RGB;
321 mb862xx.gdfBytesPP = 2;
323 return CONFIG_SYS_LIME_BASE;
326 #define W83782D_REG_CFG 0x40
327 #define W83782D_REG_BANK_SEL 0x4e
328 #define W83782D_REG_ADCCLK 0x4b
329 #define W83782D_REG_BEEP_CTRL 0x4d
330 #define W83782D_REG_BEEP_CTRL2 0x57
331 #define W83782D_REG_PWMOUT1 0x5b
332 #define W83782D_REG_VBAT 0x5d
334 static int w83782d_hwmon_init(void)
338 if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
341 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
342 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
343 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
345 buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
346 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
348 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
349 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
350 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
352 buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
353 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
354 (buf & 0xf4) | 0x01);
358 static void board_backlight_brightness(int br)
365 if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
368 buf = old_buf & 0xf8;
370 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
374 /* PWMOUT1 duty cycle ctrl */
375 buf = 255 / (100 / br);
376 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
380 reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
381 if (!(reg & BACKLIGHT_ENABLE));
382 out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
383 reg | BACKLIGHT_ENABLE);
386 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
390 reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
391 reg &= ~BACKLIGHT_ENABLE;
392 out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
394 /* Restore previous bank setting */
395 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
400 printf("W83782G I2C access failed\n");
403 void board_backlight_switch (int flag)
408 if (w83782d_hwmon_init())
409 printf ("hwmon IC init failed\n");
412 param = getenv("brightness");
413 rc = param ? simple_strtol(param, NULL, 10) : -1;
415 rc = DEFAULT_BRIGHTNESS;
419 board_backlight_brightness(rc);
422 #if defined(CONFIG_CONSOLE_EXTRA_INFO)
424 * Return text to be printed besides the logo.
426 void video_get_info_str (int line_number, char *info)
428 if (line_number == 1) {
429 strcpy (info, " Board: Socrates");