2 * Copyright (C) 2012 Stefan Roese <sr@denx.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/hardware.h>
29 #include <asm/arch/spr_misc.h>
30 #include <asm/arch/spr_ssp.h>
33 * FPGA program pin configuration on X600:
35 * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
36 * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
37 * 16bit serial writes via this SSP port to write the data bits into the
40 #define CONFIG_SYS_FPGA_PROG 2
41 #define CONFIG_SYS_FPGA_DONE 3
44 * Set the active-low FPGA reset signal.
46 static void fpga_reset(int assert)
49 * On x600 we have no means to toggle the FPGA reset signal
51 debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
55 * Set the FPGA's active-low SelectMap program line to the specified level
57 static int fpga_pgm_fn(int assert, int flush, int cookie)
59 debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
61 gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
67 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
70 static int fpga_init_fn(int cookie)
74 debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
77 * On x600, the FPGA INIT signal is not connected to the SoC.
78 * We can't read the INIT status. Let's return the "correct"
79 * INIT signal state generated via a local state-machine.
90 * Test the state of the active-high FPGA DONE pin
92 static int fpga_done_fn(int cookie)
94 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
97 * Wait for Tx-FIFO to become empty before looking for DONE
99 while (!(readl(&ssp->sspsr) & SSPSR_TFE))
102 if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
109 * FPGA pre-configuration function. Just make sure that
110 * FPGA reset is asserted to keep the FPGA from starting up after
113 static int fpga_pre_config_fn(int cookie)
115 debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
122 * FPGA post configuration function. Blip the FPGA reset line and then see if
123 * the FPGA appears to be running.
125 static int fpga_post_config_fn(int cookie)
129 debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
139 static int fpga_clk_fn(int assert_clk, int flush, int cookie)
142 * No dedicated clock signal on x600 (data & clock generated)
143 * in SSP interface. So we don't have to do anything here.
148 static int fpga_wr_fn(int assert_write, int flush, int cookie)
150 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
155 * First collect 16 bits of data
162 * If 16 bits are not available, return for more bits
171 * Wait for Tx-FIFO to become ready
173 while (!(readl(&ssp->sspsr) & SSPSR_TNF))
176 /* Send 16 bits to FPGA via SSP bus */
177 writel(data, &ssp->sspdr);
182 static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
192 static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
193 XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
197 * Initialize the SelectMap interface. We assume that the mode and the
198 * initial state of all of the port pins have already been set!
200 static void fpga_serialslave_init(void)
202 debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
203 fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
206 static int expi_setup(int freq)
208 struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
209 int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
211 pll2_m = (freq * 2) / 1000;
218 * Disable reset, Low compression, Disable retiming, Enable Expi,
219 * Enable soft reset, DMA, PLL2, Internal
221 writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
222 EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
223 EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
224 &misc->expi_clk_cfg);
227 * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
228 * Enable PLL2, Disable reset
230 writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
231 writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
232 PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
237 clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
243 * Initialize the fpga
245 int x600_init_fpga(void)
247 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
248 struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
250 /* Enable SSP2 clock */
251 writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
252 &misc->periph1_clken);
254 /* Set EXPI clock to 45 MHz */
257 /* Configure GPIO directions */
258 gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
259 gpio_direction_input(CONFIG_SYS_FPGA_DONE);
261 writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
262 writel(SSPCR1_SSE, &ssp->sspcr1);
265 * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
268 * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
269 * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
271 writel(2, &ssp->sspcpsr);
274 fpga_serialslave_init();
276 debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
277 fpga_add(fpga_xilinx, &fpga[0]);