2 * Copyright (C) 2012 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/spr_misc.h>
14 #include <asm/arch/spr_ssp.h>
17 * FPGA program pin configuration on X600:
19 * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
20 * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
21 * 16bit serial writes via this SSP port to write the data bits into the
24 #define CONFIG_SYS_FPGA_PROG 2
25 #define CONFIG_SYS_FPGA_DONE 3
28 * Set the active-low FPGA reset signal.
30 static void fpga_reset(int assert)
33 * On x600 we have no means to toggle the FPGA reset signal
35 debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
39 * Set the FPGA's active-low SelectMap program line to the specified level
41 static int fpga_pgm_fn(int assert, int flush, int cookie)
43 debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
45 gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
51 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
54 static int fpga_init_fn(int cookie)
58 debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
61 * On x600, the FPGA INIT signal is not connected to the SoC.
62 * We can't read the INIT status. Let's return the "correct"
63 * INIT signal state generated via a local state-machine.
74 * Test the state of the active-high FPGA DONE pin
76 static int fpga_done_fn(int cookie)
78 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
81 * Wait for Tx-FIFO to become empty before looking for DONE
83 while (!(readl(&ssp->sspsr) & SSPSR_TFE))
86 if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
93 * FPGA pre-configuration function. Just make sure that
94 * FPGA reset is asserted to keep the FPGA from starting up after
97 static int fpga_pre_config_fn(int cookie)
99 debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
106 * FPGA post configuration function. Blip the FPGA reset line and then see if
107 * the FPGA appears to be running.
109 static int fpga_post_config_fn(int cookie)
113 debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
123 static int fpga_clk_fn(int assert_clk, int flush, int cookie)
126 * No dedicated clock signal on x600 (data & clock generated)
127 * in SSP interface. So we don't have to do anything here.
132 static int fpga_wr_fn(int assert_write, int flush, int cookie)
134 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
139 * First collect 16 bits of data
146 * If 16 bits are not available, return for more bits
155 * Wait for Tx-FIFO to become ready
157 while (!(readl(&ssp->sspsr) & SSPSR_TNF))
160 /* Send 16 bits to FPGA via SSP bus */
161 writel(data, &ssp->sspdr);
166 static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
176 static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
177 XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
181 * Initialize the SelectMap interface. We assume that the mode and the
182 * initial state of all of the port pins have already been set!
184 static void fpga_serialslave_init(void)
186 debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
187 fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
190 static int expi_setup(int freq)
192 struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
193 int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
195 pll2_m = (freq * 2) / 1000;
202 * Disable reset, Low compression, Disable retiming, Enable Expi,
203 * Enable soft reset, DMA, PLL2, Internal
205 writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
206 EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
207 EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
208 &misc->expi_clk_cfg);
211 * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
212 * Enable PLL2, Disable reset
214 writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
215 writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
216 PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
221 clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
227 * Initialize the fpga
229 int x600_init_fpga(void)
231 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
232 struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
234 /* Enable SSP2 clock */
235 writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
236 &misc->periph1_clken);
238 /* Set EXPI clock to 45 MHz */
241 /* Configure GPIO directions */
242 gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
243 gpio_direction_input(CONFIG_SYS_FPGA_DONE);
245 writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
246 writel(SSPCR1_SSE, &ssp->sspcr1);
249 * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
252 * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
253 * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
255 writel(2, &ssp->sspcpsr);
258 fpga_serialslave_init();
260 debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
261 fpga_add(fpga_xilinx, &fpga[0]);