2 * Altera SoCFPGA SDRAM configuration
4 * SPDX-License-Identifier: BSD-3-Clause
7 #ifndef __SOCFPGA_SDRAM_CONFIG_H__
8 #define __SOCFPGA_SDRAM_CONFIG_H__
10 /* SDRAM configuration */
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
19 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
22 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
23 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
24 #define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
25 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
26 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
27 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
28 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
29 #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
32 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
34 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
35 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
36 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
37 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
38 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
39 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
40 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
41 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
42 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
43 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
44 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
45 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
46 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
47 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
48 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
49 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
50 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
51 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
52 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
53 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
54 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
55 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
56 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
57 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
58 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
59 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
60 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
61 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
62 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
63 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
64 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
65 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
66 #define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
67 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
68 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
69 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
70 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
71 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
72 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
73 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
74 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
75 #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
76 #define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
77 #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
78 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
79 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
80 #define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
82 /* Sequencer auto configuration */
83 #define RW_MGR_ACTIVATE_0_AND_1 0x0D
84 #define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
85 #define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
86 #define RW_MGR_ACTIVATE_1 0x0F
87 #define RW_MGR_CLEAR_DQS_ENABLE 0x49
88 #define RW_MGR_GUARANTEED_READ 0x4C
89 #define RW_MGR_GUARANTEED_READ_CONT 0x54
90 #define RW_MGR_GUARANTEED_WRITE 0x18
91 #define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
92 #define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
93 #define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
94 #define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
95 #define RW_MGR_IDLE 0x00
96 #define RW_MGR_IDLE_LOOP1 0x7B
97 #define RW_MGR_IDLE_LOOP2 0x7A
98 #define RW_MGR_INIT_RESET_0_CKE_0 0x6F
99 #define RW_MGR_INIT_RESET_1_CKE_0 0x74
100 #define RW_MGR_LFSR_WR_RD_BANK_0 0x22
101 #define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
102 #define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
103 #define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
104 #define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
105 #define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
106 #define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
107 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
108 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
109 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
110 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
111 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
112 #define RW_MGR_MRS0_DLL_RESET 0x02
113 #define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
114 #define RW_MGR_MRS0_USER 0x07
115 #define RW_MGR_MRS0_USER_MIRR 0x0C
116 #define RW_MGR_MRS1 0x03
117 #define RW_MGR_MRS1_MIRR 0x09
118 #define RW_MGR_MRS2 0x04
119 #define RW_MGR_MRS2_MIRR 0x0A
120 #define RW_MGR_MRS3 0x05
121 #define RW_MGR_MRS3_MIRR 0x0B
122 #define RW_MGR_PRECHARGE_ALL 0x12
123 #define RW_MGR_READ_B2B 0x59
124 #define RW_MGR_READ_B2B_WAIT1 0x61
125 #define RW_MGR_READ_B2B_WAIT2 0x6B
126 #define RW_MGR_REFRESH_ALL 0x14
127 #define RW_MGR_RETURN 0x01
128 #define RW_MGR_SGLE_READ 0x7D
129 #define RW_MGR_ZQCL 0x06
131 /* Sequencer defines configuration */
132 #define AFI_RATE_RATIO 1
133 #define CALIB_LFIFO_OFFSET 7
134 #define CALIB_VFIFO_OFFSET 5
135 #define ENABLE_SUPER_QUICK_CALIBRATION 0
136 #define IO_DELAY_PER_DCHAIN_TAP 25
137 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
138 #define IO_DELAY_PER_OPA_TAP 312
139 #define IO_DLL_CHAIN_LENGTH 8
140 #define IO_DQDQS_OUT_PHASE_MAX 0
141 #define IO_DQS_EN_DELAY_MAX 31
142 #define IO_DQS_EN_DELAY_OFFSET 0
143 #define IO_DQS_EN_PHASE_MAX 7
144 #define IO_DQS_IN_DELAY_MAX 31
145 #define IO_DQS_IN_RESERVE 4
146 #define IO_DQS_OUT_RESERVE 4
147 #define IO_IO_IN_DELAY_MAX 31
148 #define IO_IO_OUT1_DELAY_MAX 31
149 #define IO_IO_OUT2_DELAY_MAX 0
150 #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
151 #define MAX_LATENCY_COUNT_WIDTH 5
152 #define READ_VALID_FIFO_SIZE 16
153 #define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496
154 #define RW_MGR_MEM_ADDRESS_MIRRORING 0
155 #define RW_MGR_MEM_DATA_MASK_WIDTH 4
156 #define RW_MGR_MEM_DATA_WIDTH 32
157 #define RW_MGR_MEM_DQ_PER_READ_DQS 8
158 #define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
159 #define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
160 #define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
161 #define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
162 #define RW_MGR_MEM_NUMBER_OF_RANKS 1
163 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
164 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
165 #define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
166 #define TINIT_CNTR0_VAL 99
167 #define TINIT_CNTR1_VAL 32
168 #define TINIT_CNTR2_VAL 32
169 #define TRESET_CNTR0_VAL 99
170 #define TRESET_CNTR1_VAL 99
171 #define TRESET_CNTR2_VAL 10
173 /* Sequencer ac_rom_init configuration */
174 const u32 ac_rom_init[] = {
213 /* Sequencer inst_rom_init configuration */
214 const u32 inst_rom_init[] = {
344 #endif /* __SOCFPGA_SDRAM_CONFIG_H__ */