2 * Board specific setup info
5 * STMicrolelctronics, <www.st.com>
7 * (C) Copyright 2004, ARM Ltd.
8 * Philippe Robin, <philippe.robin@arm.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 /* Jump to the flash address */
35 ldr r0, =CFG_ONENAND_BASE
38 * Make it independent whether we boot from 0x0 or 0x30000000.
39 * Non-portable: it relies on the knowledge that ip has to be updated
41 orr ip, ip, r0 /* adjust return address of cpu_init_crit */
42 orr lr, lr, r0 /* adjust return address */
43 orr pc, pc, r0 /* jump to the normal address */
46 /* Initialize PLL, Remap clear, FSMC, MPMC here! */
47 /* What about GPIO, CLCD and UART */
49 /* PLL Initialization */
50 /* Prog the PLL1 @ 266 MHz ==> SDRAM Clock = 100.8 MHz */
51 ldr r0, =NOMADIK_SRC_BASE
57 /* Used to set all the timers clock to 2.4MHZ */
65 ldr r0, =NOMADIK_FSMC_BASE
67 ldr r1, =0x10DB /* For 16-bit NOR flash */
70 ldr r1, =0x03333333 /* For 16-bit NOR flash */
74 ldr r1, =0x0000105B /* BCR0 Prog control register */
77 ldr r1, =0x0A200551 /* BTR0 Prog timing register */
80 /* preload the instructions into icache */
83 mcr p15, 0, r0, c7, c13, 1
85 mcr p15, 0, r0, c7, c13, 1
88 ldr r0, =NOMADIK_SRC_BASE
100 ldr r0, =NOMADIK_SRC_BASE
105 mov r0, #(NOMADIK_FSMC_BASE & 0x10000000)
106 orr r0, r0, #(NOMADIK_FSMC_BASE & 0x0FFFFFFF)
108 ldr r1, =0x10DB /* For 16-bit NOR flash */
111 ldr r1, =0x03333333 /* For 16-bit NOR flash */
115 ldr r0, =NOMADIK_MPMC_BASE
118 str r1, [r0] /* Enable the MPMC and the DLL */
123 ldr r2, =NOMADIK_PMU_BASE
128 ldr r1, =0x1111 /* Prog the, mand delay strategy */
131 ldr r1, =0x103 /* NOP ,mand */
134 /* FIXME -- Wait required here */
136 ldr r1, =0x103 /* PALL ,mand*/
140 str r1, [r0, #0x24] /* To do at least two auto-refresh */
142 /* FIXME -- Wait required here */
144 /* Auto-refresh period = 7.8us @ SDRAM Clock = 100.8 MHz */
148 /* Prog Little Endian, Not defined in 8800 board */
154 str r1, [r0, #0x30] /* Prog tRP timing */
156 ldr r1, =0x4 /* Change for 8815 */
157 str r1, [r0, #0x34] /* Prog tRAS timing */
160 str r1, [r0, #0x38] /* Prog tSREX timing */
164 str r1, [r0, #0x44] /* Prog tWR timing */
167 str r1, [r0, #0x48] /* Prog tRC timing */
170 str r1, [r0, #0x4C] /* Prog tRFC timing */
173 str r1, [r0, #0x50] /* Prog tXSR timing */
176 str r1, [r0, #0x54] /* Prog tRRD timing */
179 str r1, [r0, #0x58] /* Prog tMRD timing */
182 str r1, [r0, #0x5C] /* Prog tCDLR timing */
184 /* DDR-SDRAM MEMORY IS ON BANK0 8815 */
185 ldr r1, =0x304 /* Prog RAS and CAS for CS 0 */
188 /* SDR-SDRAM MEMORY IS ON BANK1 8815 */
189 ldr r1, =0x304 /* Prog RAS and CAS for CS 1 */
191 /* THE DATA BUS WIDE IS PROGRAM FOR 16-BITS */
192 /* DDR-SDRAM MEMORY IS ON BANK0*/
194 ldr r1, =0x884 /* 8815 : config reg in BRC for CS0 */
197 /*SDR-SDRAM MEMORY IS ON BANK1*/
199 ldr r1, =0x884 /* 8815 : config reg in BRC for CS1 */
202 ldr r1, =0x83 /*MODE Mand*/
205 /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK0 */
207 ldr r1, =0x62000 /*Data in*/
210 /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK1 */
218 /* ENABLE ALL THE BUFFER FOR EACH AHB PORT*/
220 ldr r1, =0x01 /* Enable buffer 0 */
223 ldr r1, =0x01 /* Enable buffer 1 */
226 ldr r1, =0x01 /* Enable buffer 2 */
229 ldr r1, =0x01 /* Enable buffer 3 */
232 ldr r1, =0x01 /* Enable buffer 4 */
235 ldr r1, =0x01 /* Enable buffer 5 */
240 ldr r0, =NOMADIK_GPIO1_BASE
245 ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */
248 ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */
251 ldr r0, =NOMADIK_GPIO0_BASE
262 /* Configure CPLD_CTRL register for enabling MUX logic for UART0/UART2 */
264 ldr r0, =NOMADIK_FSMC_BASE
266 ldr r1, =0x10DB /* INIT FSMC bank 0 */
272 ldr r1, =0x010DB /* INIT FSMC bank 1 */
278 ldr r0, =NOMADIK_UART0_BASE
298 ldr r0, =NOMADIK_UART1_BASE
318 ldr r0, =NOMADIK_UART2_BASE
338 /* Configure CPLD to enable UART0 */