3 * Vikas Manocha, <vikas.manocha@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/armv7m.h>
13 #include <asm/arch/stm32.h>
14 #include <asm/arch/gpio.h>
15 #include <dm/platdata.h>
16 #include <dm/platform_data/serial_stm32x7.h>
17 #include <asm/arch/stm32_periph.h>
18 #include <asm/arch/stm32_defs.h>
19 #include <asm/arch/syscfg.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 const struct stm32_gpio_ctl gpio_ctl_gpout = {
24 .mode = STM32_GPIO_MODE_OUT,
25 .otype = STM32_GPIO_OTYPE_PP,
26 .speed = STM32_GPIO_SPEED_50M,
27 .pupd = STM32_GPIO_PUPD_NO,
31 static int fmc_setup_gpio(void)
33 clock_setup(GPIO_B_CLOCK_CFG);
34 clock_setup(GPIO_C_CLOCK_CFG);
35 clock_setup(GPIO_D_CLOCK_CFG);
36 clock_setup(GPIO_E_CLOCK_CFG);
37 clock_setup(GPIO_F_CLOCK_CFG);
38 clock_setup(GPIO_G_CLOCK_CFG);
39 clock_setup(GPIO_H_CLOCK_CFG);
50 rv = fmc_setup_gpio();
54 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
56 debug("DRAM init failed: %d\n", rv);
59 rv = ram_get_info(dev, &ram);
61 debug("Cannot get DRAM size: %d\n", rv);
64 debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
65 gd->ram_size = ram.size;
68 * Fill in global info with description of SRAM configuration
70 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
71 gd->bd->bi_dram[0].size = ram.size;
76 int uart_setup_gpio(void)
78 clock_setup(GPIO_A_CLOCK_CFG);
79 clock_setup(GPIO_B_CLOCK_CFG);
83 #ifdef CONFIG_ETH_DESIGNWARE
85 static int stmmac_setup(void)
87 clock_setup(SYSCFG_CLOCK_CFG);
89 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
91 clock_setup(GPIO_A_CLOCK_CFG);
92 clock_setup(GPIO_C_CLOCK_CFG);
93 clock_setup(GPIO_G_CLOCK_CFG);
94 clock_setup(STMMAC_CLOCK_CFG);
100 #ifdef CONFIG_STM32_QSPI
102 static int qspi_setup(void)
104 clock_setup(GPIO_B_CLOCK_CFG);
105 clock_setup(GPIO_D_CLOCK_CFG);
106 clock_setup(GPIO_E_CLOCK_CFG);
111 u32 get_board_rev(void)
116 int board_early_init_f(void)
120 res = uart_setup_gpio();
124 #ifdef CONFIG_ETH_DESIGNWARE
125 res = stmmac_setup();
130 #ifdef CONFIG_STM32_QSPI
141 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;