3 * Vikas Manocha, <vikas.manocha@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/armv7m.h>
11 #include <asm/arch/stm32.h>
12 #include <asm/arch/gpio.h>
13 #include <asm/arch/fmc.h>
14 #include <dm/platdata.h>
15 #include <dm/platform_data/serial_stm32x7.h>
16 #include <asm/arch/stm32_periph.h>
17 #include <asm/arch/stm32_defs.h>
18 #include <asm/arch/syscfg.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 const struct stm32_gpio_ctl gpio_ctl_gpout = {
23 .mode = STM32_GPIO_MODE_OUT,
24 .otype = STM32_GPIO_OTYPE_PP,
25 .speed = STM32_GPIO_SPEED_50M,
26 .pupd = STM32_GPIO_PUPD_NO,
30 const struct stm32_gpio_ctl gpio_ctl_usart = {
31 .mode = STM32_GPIO_MODE_AF,
32 .otype = STM32_GPIO_OTYPE_PP,
33 .speed = STM32_GPIO_SPEED_50M,
34 .pupd = STM32_GPIO_PUPD_UP,
38 const struct stm32_gpio_ctl gpio_ctl_fmc = {
39 .mode = STM32_GPIO_MODE_AF,
40 .otype = STM32_GPIO_OTYPE_PP,
41 .speed = STM32_GPIO_SPEED_100M,
42 .pupd = STM32_GPIO_PUPD_NO,
46 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
47 /* Chip is LQFP144, see DM00077036.pdf for details */
48 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */
49 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */
50 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */
51 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */
52 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */
53 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */
54 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */
55 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */
56 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */
57 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */
58 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */
59 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */
60 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */
61 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */
62 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */
63 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */
65 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */
66 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */
68 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */
69 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */
71 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */
72 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */
73 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */
74 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */
75 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */
76 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */
77 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */
78 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */
79 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */
80 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */
81 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */
82 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */
84 {STM32_GPIO_PORT_H, STM32_GPIO_PIN_3}, /* 136, SDRAM_NE */
85 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */
86 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */
87 {STM32_GPIO_PORT_H, STM32_GPIO_PIN_5}, /* 26, SDRAM_NWE */
88 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_3}, /* 135, SDRAM_CKE */
90 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */
93 static int fmc_setup_gpio(void)
98 clock_setup(GPIO_B_CLOCK_CFG);
99 clock_setup(GPIO_C_CLOCK_CFG);
100 clock_setup(GPIO_D_CLOCK_CFG);
101 clock_setup(GPIO_E_CLOCK_CFG);
102 clock_setup(GPIO_F_CLOCK_CFG);
103 clock_setup(GPIO_G_CLOCK_CFG);
104 clock_setup(GPIO_H_CLOCK_CFG);
106 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
107 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
117 static inline u32 _ns2clk(u32 ns, u32 freq)
119 u32 tmp = freq/1000000;
120 return (tmp * ns) / 1000;
123 #define NS2CLK(ns) (_ns2clk(ns, freq))
126 * Following are timings for IS42S16400J, from corresponding datasheet
128 #define SDRAM_CAS 3 /* 3 cycles */
129 #define SDRAM_NB 1 /* Number of banks */
130 #define SDRAM_MWID 1 /* 16 bit memory */
132 #define SDRAM_NR 0x1 /* 12-bit row */
133 #define SDRAM_NC 0x0 /* 8-bit col */
134 #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
135 #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
137 #define SDRAM_TRRD NS2CLK(12)
138 #define SDRAM_TRCD NS2CLK(18)
139 #define SDRAM_TRP NS2CLK(18)
140 #define SDRAM_TRAS NS2CLK(42)
141 #define SDRAM_TRC NS2CLK(60)
142 #define SDRAM_TRFC NS2CLK(60)
143 #define SDRAM_TCDL (1 - 1)
144 #define SDRAM_TRDL NS2CLK(12)
145 #define SDRAM_TBDL (1 - 1)
146 #define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20)
147 #define SDRAM_TCCD (1 - 1)
149 #define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */
150 #define SDRAM_TMRD 1 /* Page 10, Mode Register Set */
153 /* Last data in to row precharge, need also comply ineq on page 1648 */
154 #define SDRAM_TWR max(\
155 (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
156 (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
160 #define SDRAM_MODE_BL_SHIFT 0
161 #define SDRAM_MODE_CAS_SHIFT 4
162 #define SDRAM_MODE_BL 0
163 #define SDRAM_MODE_CAS SDRAM_CAS
170 rv = fmc_setup_gpio();
174 clock_setup(FMC_CLOCK_CFG);
177 * Get frequency for NS2CLK calculation.
179 freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
182 CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
183 | SDRAM_CAS << FMC_SDCR_CAS_SHIFT
184 | SDRAM_NB << FMC_SDCR_NB_SHIFT
185 | SDRAM_MWID << FMC_SDCR_MWID_SHIFT
186 | SDRAM_NR << FMC_SDCR_NR_SHIFT
187 | SDRAM_NC << FMC_SDCR_NC_SHIFT
188 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
189 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
190 &STM32_SDRAM_FMC->sdcr1);
193 SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
194 | SDRAM_TRP << FMC_SDTR_TRP_SHIFT
195 | SDRAM_TWR << FMC_SDTR_TWR_SHIFT
196 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT
197 | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
198 | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
199 | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
200 &STM32_SDRAM_FMC->sdtr1);
202 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
203 &STM32_SDRAM_FMC->sdcmr);
205 udelay(200); /* 200 us delay, page 10, "Power-Up" */
208 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
209 &STM32_SDRAM_FMC->sdcmr);
214 writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
215 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
220 writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
221 | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
222 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
223 &STM32_SDRAM_FMC->sdcmr);
229 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
230 &STM32_SDRAM_FMC->sdcmr);
235 writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
238 * Fill in global info with description of SRAM configuration
240 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
241 gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
243 gd->ram_size = CONFIG_SYS_RAM_SIZE;
248 static const struct stm32_gpio_dsc usart_gpio[] = {
249 {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */
250 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */
253 int uart_setup_gpio(void)
258 clock_setup(GPIO_A_CLOCK_CFG);
259 clock_setup(GPIO_B_CLOCK_CFG);
260 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
261 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
270 static const struct stm32x7_serial_platdata serial_platdata = {
271 .base = (struct stm32_usart *)USART1_BASE,
272 .clock = CONFIG_SYS_CLK_FREQ,
275 U_BOOT_DEVICE(stm32x7_serials) = {
276 .name = "serial_stm32x7",
277 .platdata = &serial_platdata,
280 #ifdef CONFIG_ETH_DESIGNWARE
281 const struct stm32_gpio_ctl gpio_ctl_eth = {
282 .mode = STM32_GPIO_MODE_AF,
283 .otype = STM32_GPIO_OTYPE_PP,
284 .speed = STM32_GPIO_SPEED_100M,
285 .pupd = STM32_GPIO_PUPD_NO,
286 .af = STM32_GPIO_AF11
289 static const struct stm32_gpio_dsc eth_gpio[] = {
290 {STM32_GPIO_PORT_A, STM32_GPIO_PIN_1}, /* ETH_RMII_REF_CLK */
291 {STM32_GPIO_PORT_A, STM32_GPIO_PIN_2}, /* ETH_MDIO */
292 {STM32_GPIO_PORT_A, STM32_GPIO_PIN_7}, /* ETH_RMII_CRS_DV */
294 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_1}, /* ETH_MDC */
295 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_4}, /* ETH_RMII_RXD0 */
296 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_5}, /* ETH_RMII_RXD1 */
298 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_11}, /* ETH_RMII_TX_EN */
299 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_13}, /* ETH_RMII_TXD0 */
300 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_14}, /* ETH_RMII_TXD1 */
303 static int stmmac_setup(void)
308 clock_setup(SYSCFG_CLOCK_CFG);
311 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
313 clock_setup(GPIO_A_CLOCK_CFG);
314 clock_setup(GPIO_C_CLOCK_CFG);
315 clock_setup(GPIO_G_CLOCK_CFG);
317 for (i = 0; i < ARRAY_SIZE(eth_gpio); i++) {
318 res = stm32_gpio_config(ð_gpio[i], &gpio_ctl_eth);
323 clock_setup(STMMAC_CLOCK_CFG);
329 #ifdef CONFIG_STM32_QSPI
330 const struct stm32_gpio_ctl gpio_ctl_qspi_9 = {
331 .mode = STM32_GPIO_MODE_AF,
332 .otype = STM32_GPIO_OTYPE_PP,
333 .speed = STM32_GPIO_SPEED_100M,
334 .pupd = STM32_GPIO_PUPD_NO,
338 const struct stm32_gpio_ctl gpio_ctl_qspi_10 = {
339 .mode = STM32_GPIO_MODE_AF,
340 .otype = STM32_GPIO_OTYPE_PP,
341 .speed = STM32_GPIO_SPEED_100M,
342 .pupd = STM32_GPIO_PUPD_NO,
343 .af = STM32_GPIO_AF10
346 static const struct stm32_gpio_dsc qspi_af9_gpio[] = {
347 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_2}, /* QUADSPI_CLK */
348 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_11}, /* QUADSPI_BK1_IO0 */
349 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_12}, /* QUADSPI_BK1_IO1 */
350 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_13}, /* QUADSPI_BK1_IO3 */
351 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_2}, /* QUADSPI_BK1_IO2 */
354 static const struct stm32_gpio_dsc qspi_af10_gpio[] = {
355 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* QUADSPI_BK1_NCS */
358 static int qspi_setup(void)
363 clock_setup(GPIO_B_CLOCK_CFG);
364 clock_setup(GPIO_D_CLOCK_CFG);
365 clock_setup(GPIO_E_CLOCK_CFG);
367 for (i = 0; i < ARRAY_SIZE(qspi_af9_gpio); i++) {
368 res = stm32_gpio_config(&qspi_af9_gpio[i], &gpio_ctl_qspi_9);
373 for (i = 0; i < ARRAY_SIZE(qspi_af10_gpio); i++) {
374 res = stm32_gpio_config(&qspi_af10_gpio[i], &gpio_ctl_qspi_10);
383 u32 get_board_rev(void)
388 int board_early_init_f(void)
392 res = uart_setup_gpio();
393 clock_setup(USART1_CLOCK_CFG);
397 #ifdef CONFIG_ETH_DESIGNWARE
398 res = stmmac_setup();
403 #ifdef CONFIG_STM32_QSPI
414 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;