2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
10 #include <asm/arch/ddr.h>
11 #include <power/pmic.h>
12 #include <power/stpmu1.h>
14 #ifdef CONFIG_PMIC_STPMU1
15 int board_ddr_power_init(void)
20 ret = uclass_get_device_by_driver(UCLASS_PMIC,
21 DM_GET_DRIVER(pmic_stpmu1), &dev);
23 /* No PMIC on board */
26 /* Set LDO3 to sync mode */
27 ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3));
31 ret &= ~STPMU1_LDO3_MODE;
32 ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
33 ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
35 ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
40 /* Set BUCK2 to 1.35V */
41 ret = pmic_clrsetbits(dev,
42 STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
43 STPMU1_BUCK_OUTPUT_MASK,
44 STPMU1_BUCK2_1350000V);
48 /* Enable BUCK2 and VREF */
49 ret = pmic_clrsetbits(dev,
50 STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
51 STPMU1_BUCK_EN, STPMU1_BUCK_EN);
55 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
57 ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG,
58 STPMU1_VREF_EN, STPMU1_VREF_EN);
62 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
65 ret = pmic_clrsetbits(dev,
66 STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
67 STPMU1_LDO_EN, STPMU1_LDO_EN);
71 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);