2 * Copyright (C) ST-Ericsson SA 2009
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <asm/types.h>
24 #include <asm/errno.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/hardware.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/prcmu.h>
31 #include "../../../drivers/mmc/arm_pl180_mmci.h"
34 #define NOMADIK_PER4_BASE (0x80150000)
35 #define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000)
36 #define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000)
38 /* Power, Reset, Clock Management Unit */
40 * SVA: Smart Video Accelerator
41 * SIA: Smart Imaging Accelerator
42 * SGA: Smart Graphic accelerator
43 * B2R2: Graphic blitter
45 #define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000)
46 #define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004)
47 #define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008)
48 #define PRCM_SIAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x00C)
49 #define PRCM_SAAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x010)
50 #define PRCM_SGACLK_MGT_REG (PRCMU_BASE + 0x014)
51 #define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
52 #define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
53 #define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
54 #define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
55 #define PRCM_SLIMCLK_MGT_REG (PRCMU_BASE + 0x028)
56 #define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
57 #define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
58 #define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
59 #define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
60 #define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
61 #define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
62 #define PRCM_DMACLK_MGT_REG (PRCMU_BASE + 0x074)
63 #define PRCM_B2R2CLK_MGT_REG (PRCMU_BASE + 0x078)
65 #define PRCM_PLLSOC0_FREQ_REG (PRCMU_BASE + 0x080)
66 #define PRCM_PLLSOC1_FREQ_REG (PRCMU_BASE + 0x084)
67 #define PRCM_PLLARM_FREQ_REG (PRCMU_BASE + 0x088)
68 #define PRCM_PLLDDR_FREQ_REG (PRCMU_BASE + 0x08C)
69 #define PRCM_ARM_CHGCLKREQ_REG (PRCMU_BASE + 0x114)
71 #define PRCM_TCR (PRCMU_BASE + 0x1C8)
74 * Memory controller register
76 #define DMC_BASE_ADDR 0x80156000
77 #define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
79 int board_id; /* set in board_late_init() */
81 /* PLLs for clock management registers */
84 PLLSOC0, /* pllsw = 001, ffs() = 1 */
85 PLLSOC1, /* pllsw = 010, ffs() = 2 */
86 PLLDDR, /* pllsw = 100, ffs() = 3 */
90 static struct pll_freq_regs {
91 int idx; /* index fror pll_name and pll_khz arrays */
94 {PLLSOC0, PRCM_PLLSOC0_FREQ_REG},
95 {PLLSOC1, PRCM_PLLSOC1_FREQ_REG},
96 {PLLDDR, PRCM_PLLDDR_FREQ_REG},
97 {PLLARM, PRCM_PLLARM_FREQ_REG},
101 static const char *pll_name[5] = {"GATED", "SOC0", "SOC1", "DDR", "ARM"};
102 static uint32_t pll_khz[5]; /* use ffs(pllsw(reg)) as index for 0..3 */
104 static struct clk_mgt_regs {
109 /* register content taken from bootrom settings */
110 {PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */
111 {PRCM_ACLK_MGT_REG, 0x0125, "ACLK"}, /* ena, SOC0/5, 160 MHz */
112 {PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */
113 {PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */
114 {PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */
115 {PRCM_SGACLK_MGT_REG, 0x0024, "SGA"}, /* dis, SOC0/4, 200 MHz */
116 {PRCM_UARTCLK_MGT_REG, 0x0300, "UART"}, /* ena, GATED, CLK38 */
117 {PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"}, /* dis, GATED, CLK38 */
118 {PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"}, /* ena, SOC0/16, 50 MHz */
119 {PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */
120 {PRCM_PER1CLK_MGT_REG, 0x126, "PER1"}, /* ena, SOC0/6, 133 MHz */
121 {PRCM_PER2CLK_MGT_REG, 0x126, "PER2"}, /* ena, SOC0/6, 133 MHz */
122 {PRCM_PER3CLK_MGT_REG, 0x126, "PER3"}, /* ena, SOC0/6, 133 MHz */
123 {PRCM_PER5CLK_MGT_REG, 0x126, "PER5"}, /* ena, SOC0/6, 133 MHz */
124 {PRCM_PER6CLK_MGT_REG, 0x126, "PER6"}, /* ena, SOC0/6, 133 MHz */
125 {PRCM_PER7CLK_MGT_REG, 0x128, "PER7"}, /* ena, SOC0/8, 100 MHz */
126 {PRCM_DMACLK_MGT_REG, 0x125, "DMA"}, /* ena, SOC0/5, 160 MHz */
127 {PRCM_B2R2CLK_MGT_REG, 0x025, "B2R2"}, /* dis, SOC0/5, 160 MHz */
131 static void init_regs(void);
133 DECLARE_GLOBAL_DATA_PTR;
134 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
135 void show_boot_progress(int progress)
137 printf("Boot reached stage %d\n", progress);
141 static unsigned int read_asicid(void)
143 unsigned int *address = (void *)U8500_BOOTROM_BASE
144 + U8500_BOOTROM_ASIC_ID_OFFSET;
145 return readl(address);
148 int cpu_is_u8500v11(void)
150 return read_asicid() == 0x008500A1;
154 * Miscellaneous platform dependent initialisations
157 int board_early_init_f(void)
165 uint32_t unused_cols_rows;
169 gd->bd->bi_arch_number = 0x1A4;
170 gd->bd->bi_boot_params = 0x00000100;
171 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
174 * Assumption: 2 CS active, both CS have same layout.
175 * 15 rows max, 11 cols max (controller spec).
176 * memory chip has 8 banks, I/O width 32 bit.
177 * The correct way would be to read MR#8: I/O width and density,
178 * but this requires locking against the PRCMU firmware.
179 * Simplified approach:
180 * Read number of unused rows and columns from mem controller.
181 * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes
183 unused_cols_rows = readl(DMC_CTL_97);
184 nrows = 15 - (unused_cols_rows & 0x07);
185 ncols = 11 - ((unused_cols_rows & 0x0700) >> 8);
186 gd->bd->bi_dram[0].size = 2 * (1 << (nrows + ncols)) * 8 * 4;
195 gd->ram_size = PHYS_SDRAM_SIZE_1;
200 unsigned int addr_vall_arr[] = {
201 0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO: Enable reqd only */
202 0x8011F008, 0x00001CFF, /* Clocks for HSI TODO: Enable reqd only */
203 0x8000F000, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
204 0x8000F008, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
205 0x80157020, 0x00000150, /* I2C 48MHz clock */
206 0x8012F000, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
207 0x8012F008, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
208 0xA03DF000, 0x0000000D, /* Clock for MTU Timers */
209 0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */
210 0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
211 0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
212 0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */
213 0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */
214 0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */
215 0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */
216 0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */
217 0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */
218 0x801571E4, 0x0000000C, /* PRCMU settings for B2R2,
219 PRCM_APE_RESETN_SET_REG */
220 0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */
221 0xA03FF000, 0x00000003, /* USB */
222 0xA03FF008, 0x00000001, /* USB */
223 0xA03FE00C, 0x00000000, /* USB */
224 0xA03FE020, 0x00000FFF, /* USB */
225 0xA03FE024, 0x00000000 /* USB */
228 #ifdef CONFIG_BOARD_LATE_INIT
231 #define LDO_VAUX3_MASK 0x3
232 #define LDO_VAUX3_ENABLE 0x1
233 #define VAUX3_VOLTAGE_2_9V 0xd
235 #define AB8500_REGU_CTRL2 0x4
236 #define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A
237 #define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421
239 static int hrefplus_mmc_power_init(void)
244 if (!cpu_is_u8500v11())
248 * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
249 * card to work. This is done by enabling the regulators in the AB8500
250 * via PRCMU I2C transactions.
252 * This code is derived from the handling of AB8500_LDO_VAUX3 in
253 * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
255 * Turn off and delay is required to have it work across soft reboots.
258 ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG);
265 ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG,
266 val & ~LDO_VAUX3_MASK);
272 /* Set the voltage to 2.9V */
273 ret = prcmu_i2c_write(AB8500_REGU_CTRL2,
274 AB8500_REGU_VRF1VAUX3_SEL_REG,
279 val = val & ~LDO_VAUX3_MASK;
280 val = val | LDO_VAUX3_ENABLE;
282 /* Turn on the supply */
283 ret = prcmu_i2c_write(AB8500_REGU_CTRL2,
284 AB8500_REGU_VRF1VAUX3_REGU_REG, val);
291 * called after all initialisation were done, but before the generic
294 int board_late_init(void)
299 * Determine and set board_id environment variable
300 * 0: mop500, 1: href500
301 * Above boards have different GPIO expander chips which we can
302 * distinguish by the chip id.
304 * The board_id environment variable is needed for the Linux bootargs.
306 (void) i2c_set_bus_num(0);
307 (void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1);
310 setenv("board_id", "0");
313 setenv("board_id", "1");
316 hrefplus_mmc_power_init();
319 * config extended GPIO pins for level shifter and
325 (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x89, 1, &byte, 1);
326 (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x83, 1, &byte, 1);
329 /* set the direction of GPIO KPY9 and KPY10 */
331 (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC8, 1, &byte, 1);
332 /* must be a multibyte access */
333 (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC4, 1,
334 (uchar []) {0x06, 0x06}, 2);
336 #endif /* CONFIG_MMC */
338 * Create a memargs variable which points uses either the memargs256 or
339 * memargs512 environment variable, depending on the memory size.
340 * memargs is used to build the bootargs, memargs256 and memargs512 are
341 * stored in the environment.
343 if (gd->bd->bi_dram[0].size == 0x10000000) {
344 setenv("memargs", "setenv bootargs ${bootargs} ${memargs256}");
345 setenv("mem", "256M");
347 setenv("memargs", "setenv bootargs ${bootargs} ${memargs512}");
348 setenv("mem", "512M");
353 #endif /* CONFIG_BOARD_LATE_INIT */
355 static void early_gpio_setup(struct gpio_register *gpio_reg, u32 bits)
357 writel(readl(&gpio_reg->gpio_dats) | bits, &gpio_reg->gpio_dats);
358 writel(readl(&gpio_reg->gpio_pdis) & ~bits, &gpio_reg->gpio_pdis);
361 static void init_regs(void)
363 /* FIXME Remove magic register array settings for ED also */
364 struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE;
367 writel(1 << 17, &prcmu->tcr);
369 u8500_prcmu_enable(&prcmu->per1clk_mgt);
370 u8500_prcmu_enable(&prcmu->per2clk_mgt);
371 u8500_prcmu_enable(&prcmu->per3clk_mgt);
372 u8500_prcmu_enable(&prcmu->per5clk_mgt);
373 u8500_prcmu_enable(&prcmu->per6clk_mgt);
374 u8500_prcmu_enable(&prcmu->per7clk_mgt);
376 u8500_prcmu_enable(&prcmu->uartclk_mgt);
377 u8500_prcmu_enable(&prcmu->i2cclk_mgt);
379 u8500_prcmu_enable(&prcmu->sdmmcclk_mgt);
381 u8500_clock_enable(1, 9, -1); /* GPIO0 */
383 u8500_clock_enable(2, 11, -1); /* GPIO1 */
385 u8500_clock_enable(3, 8, -1); /* GPIO2 */
386 u8500_clock_enable(5, 1, -1); /* GPIO3 */
388 u8500_clock_enable(3, 6, 6); /* UART2 */
390 gpio_altfuncenable(GPIO_ALT_I2C_0, "I2C0");
391 u8500_clock_enable(3, 3, 3); /* I2C0 */
393 early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x60000000);
394 gpio_altfuncenable(GPIO_ALT_UART_2, "UART2");
396 early_gpio_setup((struct gpio_register *)U8500_GPIO_6_BASE, 0x0000ffe0);
397 gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC");
399 early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x0000ffe0);
400 gpio_altfuncenable(GPIO_ALT_SD_CARD0, "SDCARD");
402 u8500_clock_enable(1, 5, 5); /* SDI0 */
403 u8500_clock_enable(2, 4, 2); /* SDI4 */
405 u8500_clock_enable(6, 7, -1); /* MTU0 */
406 u8500_clock_enable(3, 4, 4); /* SDI2 */
408 early_gpio_setup((struct gpio_register *)U8500_GPIO_4_BASE, 0x000007ff);
409 gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC");
412 * Enabling clocks for all devices which are AMBA devices in the
413 * kernel. Otherwise they will not get probe()'d because the
414 * peripheral ID register will not be powered.
417 /* XXX: some of these differ between ED/V1 */
419 u8500_clock_enable(1, 1, 1); /* UART1 */
420 u8500_clock_enable(1, 0, 0); /* UART0 */
422 u8500_clock_enable(3, 2, 2); /* SSP1 */
423 u8500_clock_enable(3, 1, 1); /* SSP0 */
425 u8500_clock_enable(2, 8, -1); /* SPI0 */
426 u8500_clock_enable(2, 5, 3); /* MSP2 */
430 static int u8500_mmci_board_init(void)
432 enum gpio_error error;
433 struct gpio_register *gpio_base_address;
435 gpio_base_address = (void *)(U8500_GPIO_0_BASE);
436 gpio_base_address->gpio_dats |= 0xFFC0000;
437 gpio_base_address->gpio_pdis &= ~0xFFC0000;
439 /* save the GPIO0 AFSELA register */
440 error = gpio_altfuncenable(GPIO_ALT_SD_CARD0, "MMC");
441 if (error != GPIO_OK) {
442 printf("u8500_mmci_board_init() gpio_altfuncenable failed\n");
448 int board_mmc_init(bd_t *bd)
450 if (u8500_mmci_board_init())
453 if (arm_pl180_mmci_init())
461 * get_pll_freq_khz - return PLL frequency in kHz
463 static uint32_t get_pll_freq_khz(uint32_t inclk_khz, uint32_t freq_reg)
465 uint32_t idf, ldf, odf, seldiv, phi;
468 * PLLOUTCLK = PHI = (INCLK*LDF)/(2*ODF*IDF) if SELDIV2=0
469 * PLLOUTCLK = PHI = (INCLK*LDF)/(4*ODF*IDF) if SELDIV2=1
471 * IDF=R(2:0) (when R=000, IDF=1d)
472 * LDF = 2*D(7:0) (D must be greater than or equal to 6)
473 * ODF = N(5:0) (when N=000000, 0DF=1d)
476 idf = (freq_reg & 0x70000) >> 16;
477 ldf = (freq_reg & 0xff) * 2;
478 odf = (freq_reg & 0x3f00) >> 8;
479 seldiv = (freq_reg & 0x01000000) >> 24;
480 phi = (inclk_khz * ldf) / (2 * odf * idf);
487 int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
492 unsigned int clk_sel;
493 struct clk_mgt_regs *clks = clk_mgt_regs;
494 struct pll_freq_regs *plls = pll_freq_regs;
497 * Go through list of PLLs.
498 * Initialise pll out frequency array (pll_khz) and print frequency.
500 inclk_khz = 38400; /* 38.4 MHz */
502 reg = readl(plls->addr);
503 phi = get_pll_freq_khz(inclk_khz, reg);
504 pll_khz[plls->idx] = phi;
505 printf("%s PLL out frequency: %d.%d Mhz\n",
506 pll_name[plls->idx], phi/1000, phi % 1000);
510 /* check ARM clock source */
511 reg = readl(PRCM_ARM_CHGCLKREQ_REG);
512 printf("A9 running on %s\n",
513 (reg & 1) ? "external clock" : "ARM PLL");
515 /* go through list of clk_mgt_reg */
516 printf("\n%19s %9s %7s %9s enabled\n",
517 "name(addr)", "value", "PLL", "CLK[MHz]");
519 reg = readl(clks->addr);
521 /* convert bit position into array index */
522 clk_sel = ffs((reg >> 5) & 0x7); /* PLLSW[2:0] */
525 clk_khz = 38400; /* CLK38 is set */
526 else if ((reg & 0x1f) == 0)
527 /* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */
530 clk_khz = pll_khz[clk_sel] / (reg & 0x1f);
532 printf("%9s(%08x): %08x, %6s, %4d.%03d, %s\n",
533 clks->descr, clks->addr, reg, pll_name[clk_sel],
534 clk_khz / 1000, clk_khz % 1000,
535 (reg & 0x100) ? "ena" : "dis");
543 clkinfo, 1, 1, do_clkinfo,