2 * (C) Copyright 2003, Embedded Edge, LLC
3 * Dan Malek, <dan@embeddededge.com>
5 * Updates for Silicon Tx GP3 8560
7 * (C) Copyright 2003,Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
12 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/processor.h>
20 #include <asm/immap_85xx.h>
21 #include <asm/fsl_ddr_sdram.h>
24 #include <spd_sdram.h>
28 * I/O Port configuration table
30 * if conf is 1, then that port pin will be configured at boot time
31 * according to the five values podr/pdir/ppar/psor/pdat for that entry
34 const iop_conf_t iop_conf_tab[4][32] = {
36 /* Port A configuration */
37 { /* conf ppar psor pdir podr pdat */
38 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
39 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
40 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
41 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
42 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
43 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
44 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
45 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
46 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
47 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
48 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
49 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
50 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
51 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
52 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
53 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
54 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
55 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
56 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
57 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
58 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
59 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
60 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
61 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
62 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
63 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
64 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
65 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
66 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
67 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
68 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
69 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
72 /* Port B configuration */
73 { /* conf ppar psor pdir podr pdat */
74 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
75 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
76 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
77 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
78 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
79 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
80 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
81 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
82 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
83 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
84 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
85 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
86 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
87 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
88 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
89 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
90 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
91 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
92 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
93 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
94 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
95 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
96 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
97 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
98 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
99 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
100 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
101 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
102 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
103 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
104 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
105 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
109 { /* conf ppar psor pdir podr pdat */
110 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
111 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
112 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
113 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
114 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
115 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
116 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
117 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
118 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
119 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
120 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
121 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
122 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
123 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
124 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
125 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
126 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
127 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
128 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
129 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
130 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
131 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
132 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
133 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
134 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
135 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
136 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
137 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
138 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
139 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
140 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
141 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
145 { /* conf ppar psor pdir podr pdat */
146 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
147 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
148 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
149 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
150 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
151 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
152 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
153 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
154 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
155 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
156 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
157 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
158 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
159 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
160 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
161 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
162 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
163 /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
164 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
165 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
166 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
167 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
168 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
169 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
170 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
171 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
172 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
173 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
174 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
175 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
176 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
177 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
181 static uint64_t next_led_update;
185 board_early_init_f(void)
187 #if defined(CONFIG_PCI)
188 volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
190 pci->peer &= 0xfffffffdf; /* disable master abort */
198 volatile uint *blatch;
200 blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
202 /* reset Giga bit Ethernet port if needed here */
204 *blatch &= ~0x000000c0;
206 *blatch = 0x000000c1; /* Light one led, too */
209 #if 0 /* This is the port we really want to use for debugging. */
210 /* reset the CPM FEC port */
211 #if (CONFIG_ETHER_INDEX == 2)
212 bcsr->bcsr2 &= ~FETH2_RST;
214 bcsr->bcsr2 |= FETH2_RST;
216 #elif (CONFIG_ETHER_INDEX == 3)
217 bcsr->bcsr3 &= ~FETH3_RST;
219 bcsr->bcsr3 |= FETH3_RST;
222 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
224 miiphy_reset("FCC1", 0x0);
226 /* change PHY address to 0x02 */
227 bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
229 bb_miiphy_write(NULL, 0x02, MII_BMCR,
230 BMCR_ANENABLE | BMCR_ANRESTART);
231 #endif /* CONFIG_MII */
238 printf ("Board: Silicon Tx GPPP 8560 Board\n");
242 /* Blinkin' LEDS for Robert.
245 show_activity(int flag)
247 volatile uint *blatch;
249 if (next_led_update > get_ticks())
252 blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
257 *blatch = (0xc0 | led_bit);
259 next_led_update += (get_tbclk() / 4);
263 #if defined(CONFIG_SYS_DRAM_TEST)
266 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
267 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
270 printf("SDRAM test phase 1:\n");
271 for (p = pstart; p < pend; p++)
274 for (p = pstart; p < pend; p++) {
275 if (*p != 0xaaaaaaaa) {
276 printf ("SDRAM test fails at: %08x\n", (uint) p);
281 printf("SDRAM test phase 2:\n");
282 for (p = pstart; p < pend; p++)
285 for (p = pstart; p < pend; p++) {
286 if (*p != 0x55555555) {
287 printf ("SDRAM test fails at: %08x\n", (uint) p);
292 printf("SDRAM test passed.\n");
297 #if defined(CONFIG_PCI)
300 * Initialize PCI Devices, report devices found.
303 #ifndef CONFIG_PCI_PNP
304 static struct pci_config_table pci_stxgp3_config_table[] = {
305 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
306 PCI_IDSEL_NUMBER, PCI_ANY_ID,
307 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
309 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
316 static struct pci_controller hose = {
317 #ifndef CONFIG_PCI_PNP
318 config_table: pci_stxgp3_config_table,
322 #endif /* CONFIG_PCI */
329 pci_mpc85xx_init(&hose);
330 #endif /* CONFIG_PCI */