4 default " Allwinner Technology"
6 # FIXME: Should not redefine these Kconfig symbols
7 config PRE_CONSOLE_BUFFER
10 config SPL_GPIO_SUPPORT
13 config SPL_LIBCOMMON_SUPPORT
16 config SPL_LIBDISK_SUPPORT
19 config SPL_LIBGENERIC_SUPPORT
22 config SPL_MMC_SUPPORT
23 depends on SPL && GENERIC_MMC
26 config SPL_POWER_SUPPORT
29 config SPL_SERIAL_SUPPORT
32 config SUNXI_HIGH_SRAM
36 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
37 with the first SRAM region being located at address 0.
38 Some newer SoCs map the boot ROM at address 0 instead and move the
39 SRAM to 64KB, just behind the mask ROM.
40 Chips using the latter setup are supposed to select this option to
41 adjust the addresses accordingly.
43 # Note only one of these may be selected at a time! But hidden choices are
44 # not supported by Kconfig
45 config SUNXI_GEN_SUN4I
48 Select this for sunxi SoCs which have resets and clocks set up
49 as the original A10 (mach-sun4i).
51 config SUNXI_GEN_SUN6I
54 Select this for sunxi SoCs which have sun6i like periphery, like
55 separate ahb reset control registers, custom pmic bus, new style
59 config MACH_SUNXI_H3_H5
61 select SUNXI_GEN_SUN6I
65 prompt "Sunxi SoC Variant"
69 bool "sun4i (Allwinner A10)"
71 select ARM_CORTEX_CPU_IS_UP
72 select SUNXI_GEN_SUN4I
76 bool "sun5i (Allwinner A13)"
78 select ARM_CORTEX_CPU_IS_UP
79 select SUNXI_GEN_SUN4I
83 bool "sun6i (Allwinner A31)"
85 select CPU_V7_HAS_NONSEC
86 select CPU_V7_HAS_VIRT
87 select ARCH_SUPPORT_PSCI
88 select SUNXI_GEN_SUN6I
90 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
93 bool "sun7i (Allwinner A20)"
95 select CPU_V7_HAS_NONSEC
96 select CPU_V7_HAS_VIRT
97 select ARCH_SUPPORT_PSCI
98 select SUNXI_GEN_SUN4I
100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
102 config MACH_SUN8I_A23
103 bool "sun8i (Allwinner A23)"
105 select CPU_V7_HAS_NONSEC
106 select CPU_V7_HAS_VIRT
107 select ARCH_SUPPORT_PSCI
108 select SUNXI_GEN_SUN6I
110 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
112 config MACH_SUN8I_A33
113 bool "sun8i (Allwinner A33)"
115 select CPU_V7_HAS_NONSEC
116 select CPU_V7_HAS_VIRT
117 select ARCH_SUPPORT_PSCI
118 select SUNXI_GEN_SUN6I
120 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
122 config MACH_SUN8I_A83T
123 bool "sun8i (Allwinner A83T)"
125 select SUNXI_GEN_SUN6I
129 bool "sun8i (Allwinner H3)"
131 select CPU_V7_HAS_NONSEC
132 select CPU_V7_HAS_VIRT
133 select ARCH_SUPPORT_PSCI
134 select MACH_SUNXI_H3_H5
135 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
138 bool "sun9i (Allwinner A80)"
140 select SUNXI_HIGH_SRAM
141 select SUNXI_GEN_SUN6I
145 bool "sun50i (Allwinner A64)"
147 select SUNXI_GEN_SUN6I
148 select SUNXI_HIGH_SRAM
151 config MACH_SUN50I_H5
152 bool "sun50i (Allwinner H5)"
154 select MACH_SUNXI_H3_H5
155 select SUNXI_HIGH_SRAM
159 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
162 default y if MACH_SUN8I_A23
163 default y if MACH_SUN8I_A33
164 default y if MACH_SUN8I_A83T
165 default y if MACH_SUNXI_H3_H5
167 config RESERVE_ALLWINNER_BOOT0_HEADER
168 bool "reserve space for Allwinner boot0 header"
169 select ENABLE_ARM_SOC_BOOT0_HOOK
171 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
172 filled with magic values post build. The Allwinner provided boot0
173 blob relies on this information to load and execute U-Boot.
174 Only needed on 64-bit Allwinner boards so far when using boot0.
176 config ARM_BOOT_HOOK_RMR
180 select ENABLE_ARM_SOC_BOOT0_HOOK
182 Insert some ARM32 code at the very beginning of the U-Boot binary
183 which uses an RMR register write to bring the core into AArch64 mode.
184 The very first instruction acts as a switch, since it's carefully
185 chosen to be a NOP in one mode and a branch in the other, so the
186 code would only be executed if not already in AArch64.
187 This allows both the SPL and the U-Boot proper to be entered in
188 either mode and switch to AArch64 if needed.
191 int "sunxi dram type"
192 depends on MACH_SUN8I_A83T
195 Set the dram type, 3: DDR3, 7: LPDDR3
198 int "sunxi dram clock speed"
199 default 792 if MACH_SUN9I
200 default 312 if MACH_SUN6I || MACH_SUN8I
201 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
202 default 672 if MACH_SUN50I
204 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
205 must be a multiple of 24. For the sun9i (A80), the tested values
206 (for DDR3-1600) are 312 to 792.
208 if MACH_SUN5I || MACH_SUN7I
210 int "sunxi mbus clock speed"
213 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
218 int "sunxi dram zq value"
219 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
220 default 127 if MACH_SUN7I
221 default 4145117 if MACH_SUN9I
222 default 3881915 if MACH_SUN50I
224 Set the dram zq value.
227 bool "sunxi dram odt enable"
228 default n if !MACH_SUN8I_A23
229 default y if MACH_SUN8I_A23
230 default y if MACH_SUN50I
232 Select this to enable dram odt (on die termination).
234 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
236 int "sunxi dram emr1 value"
237 default 0 if MACH_SUN4I
238 default 4 if MACH_SUN5I || MACH_SUN7I
240 Set the dram controller emr1 value.
243 hex "sunxi dram tpr3 value"
246 Set the dram controller tpr3 parameter. This parameter configures
247 the delay on the command lane and also phase shifts, which are
248 applied for sampling incoming read data. The default value 0
249 means that no phase/delay adjustments are necessary. Properly
250 configuring this parameter increases reliability at high DRAM
253 config DRAM_DQS_GATING_DELAY
254 hex "sunxi dram dqs_gating_delay value"
257 Set the dram controller dqs_gating_delay parmeter. Each byte
258 encodes the DQS gating delay for each byte lane. The delay
259 granularity is 1/4 cycle. For example, the value 0x05060606
260 means that the delay is 5 quarter-cycles for one lane (1.25
261 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
262 The default value 0 means autodetection. The results of hardware
263 autodetection are not very reliable and depend on the chip
264 temperature (sometimes producing different results on cold start
265 and warm reboot). But the accuracy of hardware autodetection
266 is usually good enough, unless running at really high DRAM
267 clocks speeds (up to 600MHz). If unsure, keep as 0.
270 prompt "sunxi dram timings"
271 default DRAM_TIMINGS_VENDOR_MAGIC
273 Select the timings of the DDR3 chips.
275 config DRAM_TIMINGS_VENDOR_MAGIC
276 bool "Magic vendor timings from Android"
278 The same DRAM timings as in the Allwinner boot0 bootloader.
280 config DRAM_TIMINGS_DDR3_1066F_1333H
281 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
283 Use the timings of the standard JEDEC DDR3-1066F speed bin for
284 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
285 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
286 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
287 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
288 that down binning to DDR3-1066F is supported (because DDR3-1066F
289 uses a bit faster timings than DDR3-1333H).
291 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
292 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
294 Use the timings of the slowest possible JEDEC speed bin for the
295 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
296 DDR3-800E, DDR3-1066G or DDR3-1333J.
303 config DRAM_ODT_CORRECTION
304 int "sunxi dram odt correction value"
307 Set the dram odt correction value (range -255 - 255). In allwinner
308 fex files, this option is found in bits 8-15 of the u32 odt_en variable
309 in the [dram] section. When bit 31 of the odt_en variable is set
310 then the correction is negative. Usually the value for this is 0.
314 default 1008000000 if MACH_SUN4I
315 default 1008000000 if MACH_SUN5I
316 default 1008000000 if MACH_SUN6I
317 default 912000000 if MACH_SUN7I
318 default 1008000000 if MACH_SUN8I
319 default 1008000000 if MACH_SUN9I
320 default 816000000 if MACH_SUN50I
322 config SYS_CONFIG_NAME
323 default "sun4i" if MACH_SUN4I
324 default "sun5i" if MACH_SUN5I
325 default "sun6i" if MACH_SUN6I
326 default "sun7i" if MACH_SUN7I
327 default "sun8i" if MACH_SUN8I
328 default "sun9i" if MACH_SUN9I
329 default "sun50i" if MACH_SUN50I
338 bool "UART0 on MicroSD breakout board"
341 Repurpose the SD card slot for getting access to the UART0 serial
342 console. Primarily useful only for low level u-boot debugging on
343 tablets, where normal UART0 is difficult to access and requires
344 device disassembly and/or soldering. As the SD card can't be used
345 at the same time, the system can be only booted in the FEL mode.
346 Only enable this if you really know what you are doing.
348 config OLD_SUNXI_KERNEL_COMPAT
349 bool "Enable workarounds for booting old kernels"
352 Set this to enable various workarounds for old kernels, this results in
353 sub-optimal settings for newer kernels, only enable if needed.
356 string "MAC power pin"
359 Set the pin used to power the MAC. This takes a string in the format
360 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
363 string "Card detect pin for mmc0"
364 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
367 Set the card detect pin for mmc0, leave empty to not use cd. This
368 takes a string in the format understood by sunxi_name_to_gpio, e.g.
369 PH1 for pin 1 of port H.
372 string "Card detect pin for mmc1"
375 See MMC0_CD_PIN help text.
378 string "Card detect pin for mmc2"
381 See MMC0_CD_PIN help text.
384 string "Card detect pin for mmc3"
387 See MMC0_CD_PIN help text.
390 string "Pins for mmc1"
393 Set the pins used for mmc1, when applicable. This takes a string in the
394 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
397 string "Pins for mmc2"
400 See MMC1_PINS help text.
403 string "Pins for mmc3"
406 See MMC1_PINS help text.
408 config MMC_SUNXI_SLOT_EXTRA
409 int "mmc extra slot number"
412 sunxi builds always enable mmc0, some boards also have a second sdcard
413 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
416 config INITIAL_USB_SCAN_DELAY
417 int "delay initial usb scan by x ms to allow builtin devices to init"
420 Some boards have on board usb devices which need longer than the
421 USB spec's 1 second to connect from board powerup. Set this config
422 option to a non 0 value to add an extra delay before the first usb
426 string "Vbus enable pin for usb0 (otg)"
429 Set the Vbus enable pin for usb0 (otg). This takes a string in the
430 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
433 string "Vbus detect pin for usb0 (otg)"
436 Set the Vbus detect pin for usb0 (otg). This takes a string in the
437 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
440 string "ID detect pin for usb0 (otg)"
443 Set the ID detect pin for usb0 (otg). This takes a string in the
444 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
447 string "Vbus enable pin for usb1 (ehci0)"
448 default "PH6" if MACH_SUN4I || MACH_SUN7I
449 default "PH27" if MACH_SUN6I
451 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
452 a string in the format understood by sunxi_name_to_gpio, e.g.
453 PH1 for pin 1 of port H.
456 string "Vbus enable pin for usb2 (ehci1)"
457 default "PH3" if MACH_SUN4I || MACH_SUN7I
458 default "PH24" if MACH_SUN6I
460 See USB1_VBUS_PIN help text.
463 string "Vbus enable pin for usb3 (ehci2)"
466 See USB1_VBUS_PIN help text.
469 bool "Enable I2C/TWI controller 0"
470 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
471 default n if MACH_SUN6I || MACH_SUN8I
474 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
475 its clock and setting up the bus. This is especially useful on devices
476 with slaves connected to the bus or with pins exposed through e.g. an
477 expansion port/header.
480 bool "Enable I2C/TWI controller 1"
484 See I2C0_ENABLE help text.
487 bool "Enable I2C/TWI controller 2"
491 See I2C0_ENABLE help text.
493 if MACH_SUN6I || MACH_SUN7I
495 bool "Enable I2C/TWI controller 3"
499 See I2C0_ENABLE help text.
504 bool "Enable the PRCM I2C/TWI controller"
505 # This is used for the pmic on H3
506 default y if SY8106A_POWER
509 Set this to y to enable the I2C controller which is part of the PRCM.
514 bool "Enable I2C/TWI controller 4"
518 See I2C0_ENABLE help text.
522 bool "Enable support for gpio-s on axp PMICs"
525 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
528 bool "Enable graphical uboot console on HDMI, LCD or VGA"
529 depends on !MACH_SUN8I_A83T
530 depends on !MACH_SUNXI_H3_H5
531 depends on !MACH_SUN9I
532 depends on !MACH_SUN50I
535 Say Y here to add support for using a cfb console on the HDMI, LCD
536 or VGA output found on most sunxi devices. See doc/README.video for
537 info on how to select the video output and mode.
540 bool "HDMI output support"
541 depends on VIDEO && !MACH_SUN8I
544 Say Y here to add support for outputting video over HDMI.
547 bool "VGA output support"
548 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
551 Say Y here to add support for outputting video over VGA.
553 config VIDEO_VGA_VIA_LCD
554 bool "VGA via LCD controller support"
555 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
558 Say Y here to add support for external DACs connected to the parallel
559 LCD interface driving a VGA connector, such as found on the
562 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
563 bool "Force sync active high for VGA via LCD controller support"
564 depends on VIDEO_VGA_VIA_LCD
567 Say Y here if you've a board which uses opendrain drivers for the vga
568 hsync and vsync signals. Opendrain drivers cannot generate steep enough
569 positive edges for a stable video output, so on boards with opendrain
570 drivers the sync signals must always be active high.
572 config VIDEO_VGA_EXTERNAL_DAC_EN
573 string "LCD panel power enable pin"
574 depends on VIDEO_VGA_VIA_LCD
577 Set the enable pin for the external VGA DAC. This takes a string in the
578 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
580 config VIDEO_COMPOSITE
581 bool "Composite video output support"
582 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
585 Say Y here to add support for outputting composite video.
587 config VIDEO_LCD_MODE
588 string "LCD panel timing details"
592 LCD panel timing details string, leave empty if there is no LCD panel.
593 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
594 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
595 Also see: http://linux-sunxi.org/LCD
597 config VIDEO_LCD_DCLK_PHASE
598 int "LCD panel display clock phase"
602 Select LCD panel display clock phase shift, range 0-3.
604 config VIDEO_LCD_POWER
605 string "LCD panel power enable pin"
609 Set the power enable pin for the LCD panel. This takes a string in the
610 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
612 config VIDEO_LCD_RESET
613 string "LCD panel reset pin"
617 Set the reset pin for the LCD panel. This takes a string in the format
618 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
620 config VIDEO_LCD_BL_EN
621 string "LCD panel backlight enable pin"
625 Set the backlight enable pin for the LCD panel. This takes a string in the
626 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
629 config VIDEO_LCD_BL_PWM
630 string "LCD panel backlight pwm pin"
634 Set the backlight pwm pin for the LCD panel. This takes a string in the
635 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
637 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
638 bool "LCD panel backlight pwm is inverted"
642 Set this if the backlight pwm output is active low.
644 config VIDEO_LCD_PANEL_I2C
645 bool "LCD panel needs to be configured via i2c"
650 Say y here if the LCD panel needs to be configured via i2c. This
651 will add a bitbang i2c controller using gpios to talk to the LCD.
653 config VIDEO_LCD_PANEL_I2C_SDA
654 string "LCD panel i2c interface SDA pin"
655 depends on VIDEO_LCD_PANEL_I2C
658 Set the SDA pin for the LCD i2c interface. This takes a string in the
659 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
661 config VIDEO_LCD_PANEL_I2C_SCL
662 string "LCD panel i2c interface SCL pin"
663 depends on VIDEO_LCD_PANEL_I2C
666 Set the SCL pin for the LCD i2c interface. This takes a string in the
667 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
670 # Note only one of these may be selected at a time! But hidden choices are
671 # not supported by Kconfig
672 config VIDEO_LCD_IF_PARALLEL
675 config VIDEO_LCD_IF_LVDS
680 prompt "LCD panel support"
683 Select which type of LCD panel to support.
685 config VIDEO_LCD_PANEL_PARALLEL
686 bool "Generic parallel interface LCD panel"
687 select VIDEO_LCD_IF_PARALLEL
689 config VIDEO_LCD_PANEL_LVDS
690 bool "Generic lvds interface LCD panel"
691 select VIDEO_LCD_IF_LVDS
693 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
694 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
695 select VIDEO_LCD_SSD2828
696 select VIDEO_LCD_IF_PARALLEL
698 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
700 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
701 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
702 select VIDEO_LCD_ANX9804
703 select VIDEO_LCD_IF_PARALLEL
704 select VIDEO_LCD_PANEL_I2C
706 Select this for eDP LCD panels with 4 lanes running at 1.62G,
707 connected via an ANX9804 bridge chip.
709 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
710 bool "Hitachi tx18d42vm LCD panel"
711 select VIDEO_LCD_HITACHI_TX18D42VM
712 select VIDEO_LCD_IF_LVDS
714 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
716 config VIDEO_LCD_TL059WV5C0
717 bool "tl059wv5c0 LCD panel"
718 select VIDEO_LCD_PANEL_I2C
719 select VIDEO_LCD_IF_PARALLEL
721 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
722 Aigo M60/M608/M606 tablets.
727 string "SATA power pin"
730 Set the pins used to power the SATA. This takes a string in the
731 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
735 int "GMAC Transmit Clock Delay Chain"
738 Set the GMAC Transmit Clock Delay Chain value.
740 config SPL_STACK_R_ADDR
741 default 0x4fe00000 if MACH_SUN4I
742 default 0x4fe00000 if MACH_SUN5I
743 default 0x4fe00000 if MACH_SUN6I
744 default 0x4fe00000 if MACH_SUN7I
745 default 0x4fe00000 if MACH_SUN8I
746 default 0x2fe00000 if MACH_SUN9I
747 default 0x4fe00000 if MACH_SUN50I