4 default " Allwinner Technology"
6 # FIXME: Should not redefine these Kconfig symbols
7 config PRE_CONSOLE_BUFFER
10 config SPL_GPIO_SUPPORT
13 config SPL_LIBCOMMON_SUPPORT
16 config SPL_LIBDISK_SUPPORT
19 config SPL_LIBGENERIC_SUPPORT
22 config SPL_MMC_SUPPORT
23 depends on SPL && GENERIC_MMC
26 config SPL_POWER_SUPPORT
29 config SPL_SERIAL_SUPPORT
32 config SUNXI_HIGH_SRAM
36 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
37 with the first SRAM region being located at address 0.
38 Some newer SoCs map the boot ROM at address 0 instead and move the
39 SRAM to 64KB, just behind the mask ROM.
40 Chips using the latter setup are supposed to select this option to
41 adjust the addresses accordingly.
43 # Note only one of these may be selected at a time! But hidden choices are
44 # not supported by Kconfig
45 config SUNXI_GEN_SUN4I
48 Select this for sunxi SoCs which have resets and clocks set up
49 as the original A10 (mach-sun4i).
51 config SUNXI_GEN_SUN6I
54 Select this for sunxi SoCs which have sun6i like periphery, like
55 separate ahb reset control registers, custom pmic bus, new style
59 config MACH_SUNXI_H3_H5
62 select SUNXI_GEN_SUN6I
66 prompt "Sunxi SoC Variant"
70 bool "sun4i (Allwinner A10)"
72 select ARM_CORTEX_CPU_IS_UP
73 select SUNXI_GEN_SUN4I
77 bool "sun5i (Allwinner A13)"
79 select ARM_CORTEX_CPU_IS_UP
80 select SUNXI_GEN_SUN4I
84 bool "sun6i (Allwinner A31)"
86 select CPU_V7_HAS_NONSEC
87 select CPU_V7_HAS_VIRT
88 select ARCH_SUPPORT_PSCI
89 select SUNXI_GEN_SUN6I
91 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
94 bool "sun7i (Allwinner A20)"
96 select CPU_V7_HAS_NONSEC
97 select CPU_V7_HAS_VIRT
98 select ARCH_SUPPORT_PSCI
99 select SUNXI_GEN_SUN4I
101 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
103 config MACH_SUN8I_A23
104 bool "sun8i (Allwinner A23)"
106 select CPU_V7_HAS_NONSEC
107 select CPU_V7_HAS_VIRT
108 select ARCH_SUPPORT_PSCI
109 select SUNXI_GEN_SUN6I
111 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
113 config MACH_SUN8I_A33
114 bool "sun8i (Allwinner A33)"
116 select CPU_V7_HAS_NONSEC
117 select CPU_V7_HAS_VIRT
118 select ARCH_SUPPORT_PSCI
119 select SUNXI_GEN_SUN6I
121 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
123 config MACH_SUN8I_A83T
124 bool "sun8i (Allwinner A83T)"
126 select SUNXI_GEN_SUN6I
130 bool "sun8i (Allwinner H3)"
132 select CPU_V7_HAS_NONSEC
133 select CPU_V7_HAS_VIRT
134 select ARCH_SUPPORT_PSCI
135 select MACH_SUNXI_H3_H5
136 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
138 config MACH_SUN8I_R40
139 bool "sun8i (Allwinner R40)"
141 select CPU_V7_HAS_NONSEC
142 select CPU_V7_HAS_VIRT
143 select ARCH_SUPPORT_PSCI
144 select SUNXI_GEN_SUN6I
148 bool "sun9i (Allwinner A80)"
150 select SUNXI_HIGH_SRAM
151 select SUNXI_GEN_SUN6I
155 bool "sun50i (Allwinner A64)"
158 select SUNXI_GEN_SUN6I
159 select SUNXI_HIGH_SRAM
162 config MACH_SUN50I_H5
163 bool "sun50i (Allwinner H5)"
165 select MACH_SUNXI_H3_H5
166 select SUNXI_HIGH_SRAM
170 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
173 default y if MACH_SUN8I_A23
174 default y if MACH_SUN8I_A33
175 default y if MACH_SUN8I_A83T
176 default y if MACH_SUNXI_H3_H5
177 default y if MACH_SUN8I_R40
179 config RESERVE_ALLWINNER_BOOT0_HEADER
180 bool "reserve space for Allwinner boot0 header"
181 select ENABLE_ARM_SOC_BOOT0_HOOK
183 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
184 filled with magic values post build. The Allwinner provided boot0
185 blob relies on this information to load and execute U-Boot.
186 Only needed on 64-bit Allwinner boards so far when using boot0.
188 config ARM_BOOT_HOOK_RMR
192 select ENABLE_ARM_SOC_BOOT0_HOOK
194 Insert some ARM32 code at the very beginning of the U-Boot binary
195 which uses an RMR register write to bring the core into AArch64 mode.
196 The very first instruction acts as a switch, since it's carefully
197 chosen to be a NOP in one mode and a branch in the other, so the
198 code would only be executed if not already in AArch64.
199 This allows both the SPL and the U-Boot proper to be entered in
200 either mode and switch to AArch64 if needed.
203 int "sunxi dram type"
204 depends on MACH_SUN8I_A83T
207 Set the dram type, 3: DDR3, 7: LPDDR3
210 int "sunxi dram clock speed"
211 default 792 if MACH_SUN9I
212 default 648 if MACH_SUN8I_R40
213 default 312 if MACH_SUN6I || MACH_SUN8I
214 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
215 default 672 if MACH_SUN50I
217 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
218 must be a multiple of 24. For the sun9i (A80), the tested values
219 (for DDR3-1600) are 312 to 792.
221 if MACH_SUN5I || MACH_SUN7I
223 int "sunxi mbus clock speed"
226 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
231 int "sunxi dram zq value"
232 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
233 default 127 if MACH_SUN7I
234 default 3881979 if MACH_SUN8I_R40
235 default 4145117 if MACH_SUN9I
236 default 3881915 if MACH_SUN50I
238 Set the dram zq value.
241 bool "sunxi dram odt enable"
242 default n if !MACH_SUN8I_A23
243 default y if MACH_SUN8I_A23
244 default y if MACH_SUN8I_R40
245 default y if MACH_SUN50I
247 Select this to enable dram odt (on die termination).
249 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
251 int "sunxi dram emr1 value"
252 default 0 if MACH_SUN4I
253 default 4 if MACH_SUN5I || MACH_SUN7I
255 Set the dram controller emr1 value.
258 hex "sunxi dram tpr3 value"
261 Set the dram controller tpr3 parameter. This parameter configures
262 the delay on the command lane and also phase shifts, which are
263 applied for sampling incoming read data. The default value 0
264 means that no phase/delay adjustments are necessary. Properly
265 configuring this parameter increases reliability at high DRAM
268 config DRAM_DQS_GATING_DELAY
269 hex "sunxi dram dqs_gating_delay value"
272 Set the dram controller dqs_gating_delay parmeter. Each byte
273 encodes the DQS gating delay for each byte lane. The delay
274 granularity is 1/4 cycle. For example, the value 0x05060606
275 means that the delay is 5 quarter-cycles for one lane (1.25
276 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
277 The default value 0 means autodetection. The results of hardware
278 autodetection are not very reliable and depend on the chip
279 temperature (sometimes producing different results on cold start
280 and warm reboot). But the accuracy of hardware autodetection
281 is usually good enough, unless running at really high DRAM
282 clocks speeds (up to 600MHz). If unsure, keep as 0.
285 prompt "sunxi dram timings"
286 default DRAM_TIMINGS_VENDOR_MAGIC
288 Select the timings of the DDR3 chips.
290 config DRAM_TIMINGS_VENDOR_MAGIC
291 bool "Magic vendor timings from Android"
293 The same DRAM timings as in the Allwinner boot0 bootloader.
295 config DRAM_TIMINGS_DDR3_1066F_1333H
296 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
298 Use the timings of the standard JEDEC DDR3-1066F speed bin for
299 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
300 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
301 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
302 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
303 that down binning to DDR3-1066F is supported (because DDR3-1066F
304 uses a bit faster timings than DDR3-1333H).
306 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
307 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
309 Use the timings of the slowest possible JEDEC speed bin for the
310 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
311 DDR3-800E, DDR3-1066G or DDR3-1333J.
318 config DRAM_ODT_CORRECTION
319 int "sunxi dram odt correction value"
322 Set the dram odt correction value (range -255 - 255). In allwinner
323 fex files, this option is found in bits 8-15 of the u32 odt_en variable
324 in the [dram] section. When bit 31 of the odt_en variable is set
325 then the correction is negative. Usually the value for this is 0.
329 default 1008000000 if MACH_SUN4I
330 default 1008000000 if MACH_SUN5I
331 default 1008000000 if MACH_SUN6I
332 default 912000000 if MACH_SUN7I
333 default 1008000000 if MACH_SUN8I
334 default 1008000000 if MACH_SUN9I
335 default 816000000 if MACH_SUN50I
337 config SYS_CONFIG_NAME
338 default "sun4i" if MACH_SUN4I
339 default "sun5i" if MACH_SUN5I
340 default "sun6i" if MACH_SUN6I
341 default "sun7i" if MACH_SUN7I
342 default "sun8i" if MACH_SUN8I
343 default "sun9i" if MACH_SUN9I
344 default "sun50i" if MACH_SUN50I
353 bool "UART0 on MicroSD breakout board"
356 Repurpose the SD card slot for getting access to the UART0 serial
357 console. Primarily useful only for low level u-boot debugging on
358 tablets, where normal UART0 is difficult to access and requires
359 device disassembly and/or soldering. As the SD card can't be used
360 at the same time, the system can be only booted in the FEL mode.
361 Only enable this if you really know what you are doing.
363 config OLD_SUNXI_KERNEL_COMPAT
364 bool "Enable workarounds for booting old kernels"
367 Set this to enable various workarounds for old kernels, this results in
368 sub-optimal settings for newer kernels, only enable if needed.
371 string "MAC power pin"
374 Set the pin used to power the MAC. This takes a string in the format
375 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
378 string "Card detect pin for mmc0"
379 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
382 Set the card detect pin for mmc0, leave empty to not use cd. This
383 takes a string in the format understood by sunxi_name_to_gpio, e.g.
384 PH1 for pin 1 of port H.
387 string "Card detect pin for mmc1"
390 See MMC0_CD_PIN help text.
393 string "Card detect pin for mmc2"
396 See MMC0_CD_PIN help text.
399 string "Card detect pin for mmc3"
402 See MMC0_CD_PIN help text.
405 string "Pins for mmc1"
408 Set the pins used for mmc1, when applicable. This takes a string in the
409 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
412 string "Pins for mmc2"
415 See MMC1_PINS help text.
418 string "Pins for mmc3"
421 See MMC1_PINS help text.
423 config MMC_SUNXI_SLOT_EXTRA
424 int "mmc extra slot number"
427 sunxi builds always enable mmc0, some boards also have a second sdcard
428 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
431 config INITIAL_USB_SCAN_DELAY
432 int "delay initial usb scan by x ms to allow builtin devices to init"
435 Some boards have on board usb devices which need longer than the
436 USB spec's 1 second to connect from board powerup. Set this config
437 option to a non 0 value to add an extra delay before the first usb
441 string "Vbus enable pin for usb0 (otg)"
444 Set the Vbus enable pin for usb0 (otg). This takes a string in the
445 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
448 string "Vbus detect pin for usb0 (otg)"
451 Set the Vbus detect pin for usb0 (otg). This takes a string in the
452 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
455 string "ID detect pin for usb0 (otg)"
458 Set the ID detect pin for usb0 (otg). This takes a string in the
459 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
462 string "Vbus enable pin for usb1 (ehci0)"
463 default "PH6" if MACH_SUN4I || MACH_SUN7I
464 default "PH27" if MACH_SUN6I
466 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
467 a string in the format understood by sunxi_name_to_gpio, e.g.
468 PH1 for pin 1 of port H.
471 string "Vbus enable pin for usb2 (ehci1)"
472 default "PH3" if MACH_SUN4I || MACH_SUN7I
473 default "PH24" if MACH_SUN6I
475 See USB1_VBUS_PIN help text.
478 string "Vbus enable pin for usb3 (ehci2)"
481 See USB1_VBUS_PIN help text.
484 bool "Enable I2C/TWI controller 0"
485 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
486 default n if MACH_SUN6I || MACH_SUN8I
489 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
490 its clock and setting up the bus. This is especially useful on devices
491 with slaves connected to the bus or with pins exposed through e.g. an
492 expansion port/header.
495 bool "Enable I2C/TWI controller 1"
499 See I2C0_ENABLE help text.
502 bool "Enable I2C/TWI controller 2"
506 See I2C0_ENABLE help text.
508 if MACH_SUN6I || MACH_SUN7I
510 bool "Enable I2C/TWI controller 3"
514 See I2C0_ENABLE help text.
519 bool "Enable the PRCM I2C/TWI controller"
520 # This is used for the pmic on H3
521 default y if SY8106A_POWER
524 Set this to y to enable the I2C controller which is part of the PRCM.
529 bool "Enable I2C/TWI controller 4"
533 See I2C0_ENABLE help text.
537 bool "Enable support for gpio-s on axp PMICs"
540 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
543 bool "Enable graphical uboot console on HDMI, LCD or VGA"
544 depends on !MACH_SUN8I_A83T
545 depends on !MACH_SUNXI_H3_H5
546 depends on !MACH_SUN8I_R40
547 depends on !MACH_SUN9I
548 depends on !MACH_SUN50I
551 Say Y here to add support for using a cfb console on the HDMI, LCD
552 or VGA output found on most sunxi devices. See doc/README.video for
553 info on how to select the video output and mode.
556 bool "HDMI output support"
557 depends on VIDEO && !MACH_SUN8I
560 Say Y here to add support for outputting video over HDMI.
563 bool "VGA output support"
564 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
567 Say Y here to add support for outputting video over VGA.
569 config VIDEO_VGA_VIA_LCD
570 bool "VGA via LCD controller support"
571 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
574 Say Y here to add support for external DACs connected to the parallel
575 LCD interface driving a VGA connector, such as found on the
578 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
579 bool "Force sync active high for VGA via LCD controller support"
580 depends on VIDEO_VGA_VIA_LCD
583 Say Y here if you've a board which uses opendrain drivers for the vga
584 hsync and vsync signals. Opendrain drivers cannot generate steep enough
585 positive edges for a stable video output, so on boards with opendrain
586 drivers the sync signals must always be active high.
588 config VIDEO_VGA_EXTERNAL_DAC_EN
589 string "LCD panel power enable pin"
590 depends on VIDEO_VGA_VIA_LCD
593 Set the enable pin for the external VGA DAC. This takes a string in the
594 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
596 config VIDEO_COMPOSITE
597 bool "Composite video output support"
598 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
601 Say Y here to add support for outputting composite video.
603 config VIDEO_LCD_MODE
604 string "LCD panel timing details"
608 LCD panel timing details string, leave empty if there is no LCD panel.
609 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
610 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
611 Also see: http://linux-sunxi.org/LCD
613 config VIDEO_LCD_DCLK_PHASE
614 int "LCD panel display clock phase"
618 Select LCD panel display clock phase shift, range 0-3.
620 config VIDEO_LCD_POWER
621 string "LCD panel power enable pin"
625 Set the power enable pin for the LCD panel. This takes a string in the
626 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
628 config VIDEO_LCD_RESET
629 string "LCD panel reset pin"
633 Set the reset pin for the LCD panel. This takes a string in the format
634 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
636 config VIDEO_LCD_BL_EN
637 string "LCD panel backlight enable pin"
641 Set the backlight enable pin for the LCD panel. This takes a string in the
642 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
645 config VIDEO_LCD_BL_PWM
646 string "LCD panel backlight pwm pin"
650 Set the backlight pwm pin for the LCD panel. This takes a string in the
651 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
653 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
654 bool "LCD panel backlight pwm is inverted"
658 Set this if the backlight pwm output is active low.
660 config VIDEO_LCD_PANEL_I2C
661 bool "LCD panel needs to be configured via i2c"
666 Say y here if the LCD panel needs to be configured via i2c. This
667 will add a bitbang i2c controller using gpios to talk to the LCD.
669 config VIDEO_LCD_PANEL_I2C_SDA
670 string "LCD panel i2c interface SDA pin"
671 depends on VIDEO_LCD_PANEL_I2C
674 Set the SDA pin for the LCD i2c interface. This takes a string in the
675 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
677 config VIDEO_LCD_PANEL_I2C_SCL
678 string "LCD panel i2c interface SCL pin"
679 depends on VIDEO_LCD_PANEL_I2C
682 Set the SCL pin for the LCD i2c interface. This takes a string in the
683 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
686 # Note only one of these may be selected at a time! But hidden choices are
687 # not supported by Kconfig
688 config VIDEO_LCD_IF_PARALLEL
691 config VIDEO_LCD_IF_LVDS
700 prompt "LCD panel support"
703 Select which type of LCD panel to support.
705 config VIDEO_LCD_PANEL_PARALLEL
706 bool "Generic parallel interface LCD panel"
707 select VIDEO_LCD_IF_PARALLEL
709 config VIDEO_LCD_PANEL_LVDS
710 bool "Generic lvds interface LCD panel"
711 select VIDEO_LCD_IF_LVDS
713 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
714 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
715 select VIDEO_LCD_SSD2828
716 select VIDEO_LCD_IF_PARALLEL
718 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
720 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
721 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
722 select VIDEO_LCD_ANX9804
723 select VIDEO_LCD_IF_PARALLEL
724 select VIDEO_LCD_PANEL_I2C
726 Select this for eDP LCD panels with 4 lanes running at 1.62G,
727 connected via an ANX9804 bridge chip.
729 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
730 bool "Hitachi tx18d42vm LCD panel"
731 select VIDEO_LCD_HITACHI_TX18D42VM
732 select VIDEO_LCD_IF_LVDS
734 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
736 config VIDEO_LCD_TL059WV5C0
737 bool "tl059wv5c0 LCD panel"
738 select VIDEO_LCD_PANEL_I2C
739 select VIDEO_LCD_IF_PARALLEL
741 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
742 Aigo M60/M608/M606 tablets.
747 string "SATA power pin"
750 Set the pins used to power the SATA. This takes a string in the
751 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
755 int "GMAC Transmit Clock Delay Chain"
758 Set the GMAC Transmit Clock Delay Chain value.
760 config SPL_STACK_R_ADDR
761 default 0x4fe00000 if MACH_SUN4I
762 default 0x4fe00000 if MACH_SUN5I
763 default 0x4fe00000 if MACH_SUN6I
764 default 0x4fe00000 if MACH_SUN7I
765 default 0x4fe00000 if MACH_SUN8I
766 default 0x2fe00000 if MACH_SUN9I
767 default 0x4fe00000 if MACH_SUN50I