8 #define AHCI_PHYCS0R 0x00c0
9 #define AHCI_PHYCS1R 0x00c4
10 #define AHCI_PHYCS2R 0x00c8
11 #define AHCI_RWCR 0x00fc
13 /* This magic PHY initialisation was taken from the Allwinner releases
14 * and Linux driver, but is completely undocumented.
16 static int sunxi_ahci_phy_init(u32 base)
18 u8 *reg_base = (u8 *)base;
22 writel(0, reg_base + AHCI_RWCR);
25 setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
26 clrsetbits_le32(reg_base + AHCI_PHYCS0R,
28 (0x5 << 24) | (0x1 << 23) | (0x1 << 18));
29 clrsetbits_le32(reg_base + AHCI_PHYCS1R,
30 (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
31 (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
32 setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
33 clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
34 clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
35 clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
38 setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
40 timeout = 250; /* Power up takes approx 50 us */
42 reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);
43 if (reg_val == (0x2 << 28))
46 printf("AHCI PHY power up failed.\n");
52 setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
54 timeout = 100; /* Calibration takes approx 10 us */
56 reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);
60 printf("AHCI PHY calibration failed.\n");
68 writel(0x7, reg_base + AHCI_RWCR);
75 printf("SUNXI SCSI INIT\n");
77 gpio_request(CONFIG_SATAPWR, "satapwr");
78 gpio_direction_output(CONFIG_SATAPWR, 1);
79 /* Give attached sata device time to power-up to avoid link timeouts */
83 if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
86 ahci_init((void __iomem *)SUNXI_SATA_BASE);