2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some board init for the Allwinner A10-evb board.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/display.h>
20 #include <asm/arch/dram.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc.h>
23 #include <asm/arch/spl.h>
24 #include <asm/arch/usb_phy.h>
26 #include <asm/armv7.h>
31 #include <environment.h>
37 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
38 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
39 int soft_i2c_gpio_sda;
40 int soft_i2c_gpio_scl;
42 static int soft_i2c_board_init(void)
46 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
47 if (soft_i2c_gpio_sda < 0) {
48 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
49 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
50 return soft_i2c_gpio_sda;
52 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
54 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
59 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
60 if (soft_i2c_gpio_scl < 0) {
61 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
62 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
63 return soft_i2c_gpio_scl;
65 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
67 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
75 static int soft_i2c_board_init(void) { return 0; }
78 DECLARE_GLOBAL_DATA_PTR;
80 /* add board specific code here */
83 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
85 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
88 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
89 debug("id_pfr1: 0x%08x\n", id_pfr1);
90 /* Generic Timer Extension available? */
91 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
94 debug("Setting CNTFRQ\n");
97 * CNTFRQ is a secure register, so we will crash if we try to
98 * write this from the non-secure world (read is OK, though).
99 * In case some bootcode has already set the correct value,
100 * we avoid the risk of writing to it.
102 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
103 if (freq != COUNTER_FREQUENCY) {
104 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
105 freq, COUNTER_FREQUENCY);
106 #ifdef CONFIG_NON_SECURE
107 printf("arch timer frequency is wrong, but cannot adjust it\n");
109 asm volatile("mcr p15, 0, %0, c14, c0, 0"
110 : : "r"(COUNTER_FREQUENCY));
114 #endif /* !CONFIG_ARM64 */
116 ret = axp_gpio_init();
120 #ifdef CONFIG_SATAPWR
121 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
122 gpio_request(satapwr_pin, "satapwr");
123 gpio_direction_output(satapwr_pin, 1);
126 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
127 gpio_request(macpwr_pin, "macpwr");
128 gpio_direction_output(macpwr_pin, 1);
131 /* Uses dm gpio code so do this here and not in i2c_init_board() */
132 return soft_i2c_board_init();
137 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
142 #if defined(CONFIG_NAND_SUNXI)
143 static void nand_pinmux_setup(void)
147 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
148 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
150 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
151 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
152 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
154 /* sun4i / sun7i do have a PC23, but it is not used for nand,
155 * only sun7i has a PC24 */
156 #ifdef CONFIG_MACH_SUN7I
157 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
161 static void nand_clock_setup(void)
163 struct sunxi_ccm_reg *const ccm =
164 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
166 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
167 #ifdef CONFIG_MACH_SUN9I
168 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
170 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
172 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
175 void board_nand_init(void)
179 #ifndef CONFIG_SPL_BUILD
185 #ifdef CONFIG_GENERIC_MMC
186 static void mmc_pinmux_setup(int sdc)
189 __maybe_unused int pins;
194 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
195 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
196 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
197 sunxi_gpio_set_drv(pin, 2);
202 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
204 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
205 defined(CONFIG_MACH_SUN8I_R40)
206 if (pins == SUNXI_GPIO_H) {
207 /* SDC1: PH22-PH-27 */
208 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
209 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
210 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
211 sunxi_gpio_set_drv(pin, 2);
215 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
216 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
217 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
218 sunxi_gpio_set_drv(pin, 2);
221 #elif defined(CONFIG_MACH_SUN5I)
223 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
224 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
225 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
226 sunxi_gpio_set_drv(pin, 2);
228 #elif defined(CONFIG_MACH_SUN6I)
230 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
231 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
232 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
233 sunxi_gpio_set_drv(pin, 2);
235 #elif defined(CONFIG_MACH_SUN8I)
236 if (pins == SUNXI_GPIO_D) {
238 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
239 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
240 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
241 sunxi_gpio_set_drv(pin, 2);
245 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
246 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
247 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
248 sunxi_gpio_set_drv(pin, 2);
255 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
257 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
259 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
260 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
261 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
262 sunxi_gpio_set_drv(pin, 2);
264 #elif defined(CONFIG_MACH_SUN5I)
265 if (pins == SUNXI_GPIO_E) {
267 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
268 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
269 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
270 sunxi_gpio_set_drv(pin, 2);
274 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
275 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
276 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
277 sunxi_gpio_set_drv(pin, 2);
280 #elif defined(CONFIG_MACH_SUN6I)
281 if (pins == SUNXI_GPIO_A) {
283 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
284 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
285 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
286 sunxi_gpio_set_drv(pin, 2);
289 /* SDC2: PC6-PC15, PC24 */
290 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
291 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
292 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
293 sunxi_gpio_set_drv(pin, 2);
296 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
297 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
298 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
300 #elif defined(CONFIG_MACH_SUN8I_R40)
301 /* SDC2: PC6-PC15, PC24 */
302 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
303 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
304 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
305 sunxi_gpio_set_drv(pin, 2);
308 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
309 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
310 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
311 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
312 /* SDC2: PC5-PC6, PC8-PC16 */
313 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
314 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
315 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
316 sunxi_gpio_set_drv(pin, 2);
319 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
320 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
321 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
322 sunxi_gpio_set_drv(pin, 2);
324 #elif defined(CONFIG_MACH_SUN9I)
326 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
327 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
328 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
329 sunxi_gpio_set_drv(pin, 2);
335 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
337 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
338 defined(CONFIG_MACH_SUN8I_R40)
340 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
341 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
342 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
343 sunxi_gpio_set_drv(pin, 2);
345 #elif defined(CONFIG_MACH_SUN6I)
346 if (pins == SUNXI_GPIO_A) {
348 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
349 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
350 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
351 sunxi_gpio_set_drv(pin, 2);
354 /* SDC3: PC6-PC15, PC24 */
355 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
356 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
357 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
358 sunxi_gpio_set_drv(pin, 2);
361 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
362 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
363 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
369 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
374 int board_mmc_init(bd_t *bis)
376 __maybe_unused struct mmc *mmc0, *mmc1;
377 __maybe_unused char buf[512];
379 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
380 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
384 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
385 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
386 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
391 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
393 * On systems with an emmc (mmc2), figure out if we are booting from
394 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc.
395 * are searched there first. Note we only do this for u-boot proper,
396 * not for the SPL, see spl_boot_device().
398 if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) {
399 /* Booting from emmc / mmc2, swap */
400 mmc0->block_dev.devnum = 1;
401 mmc1->block_dev.devnum = 0;
409 void i2c_init_board(void)
411 #ifdef CONFIG_I2C0_ENABLE
412 #if defined(CONFIG_MACH_SUN4I) || \
413 defined(CONFIG_MACH_SUN5I) || \
414 defined(CONFIG_MACH_SUN7I) || \
415 defined(CONFIG_MACH_SUN8I_R40)
416 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
417 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
418 clock_twi_onoff(0, 1);
419 #elif defined(CONFIG_MACH_SUN6I)
420 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
421 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
422 clock_twi_onoff(0, 1);
423 #elif defined(CONFIG_MACH_SUN8I)
424 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
425 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
426 clock_twi_onoff(0, 1);
430 #ifdef CONFIG_I2C1_ENABLE
431 #if defined(CONFIG_MACH_SUN4I) || \
432 defined(CONFIG_MACH_SUN7I) || \
433 defined(CONFIG_MACH_SUN8I_R40)
434 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
435 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
436 clock_twi_onoff(1, 1);
437 #elif defined(CONFIG_MACH_SUN5I)
438 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
439 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
440 clock_twi_onoff(1, 1);
441 #elif defined(CONFIG_MACH_SUN6I)
442 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
443 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
444 clock_twi_onoff(1, 1);
445 #elif defined(CONFIG_MACH_SUN8I)
446 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
447 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
448 clock_twi_onoff(1, 1);
452 #ifdef CONFIG_I2C2_ENABLE
453 #if defined(CONFIG_MACH_SUN4I) || \
454 defined(CONFIG_MACH_SUN7I) || \
455 defined(CONFIG_MACH_SUN8I_R40)
456 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
457 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
458 clock_twi_onoff(2, 1);
459 #elif defined(CONFIG_MACH_SUN5I)
460 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
461 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
462 clock_twi_onoff(2, 1);
463 #elif defined(CONFIG_MACH_SUN6I)
464 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
465 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
466 clock_twi_onoff(2, 1);
467 #elif defined(CONFIG_MACH_SUN8I)
468 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
469 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
470 clock_twi_onoff(2, 1);
474 #ifdef CONFIG_I2C3_ENABLE
475 #if defined(CONFIG_MACH_SUN6I)
476 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
477 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
478 clock_twi_onoff(3, 1);
479 #elif defined(CONFIG_MACH_SUN7I) || \
480 defined(CONFIG_MACH_SUN8I_R40)
481 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
482 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
483 clock_twi_onoff(3, 1);
487 #ifdef CONFIG_I2C4_ENABLE
488 #if defined(CONFIG_MACH_SUN7I) || \
489 defined(CONFIG_MACH_SUN8I_R40)
490 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
491 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
492 clock_twi_onoff(4, 1);
496 #ifdef CONFIG_R_I2C_ENABLE
497 clock_twi_onoff(5, 1);
498 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
499 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
503 #ifdef CONFIG_SPL_BUILD
504 void sunxi_board_init(void)
506 int power_failed = 0;
507 unsigned long ramsize;
509 #ifdef CONFIG_SY8106A_POWER
510 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
513 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
514 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
515 defined CONFIG_AXP818_POWER
516 power_failed = axp_init();
518 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
519 defined CONFIG_AXP818_POWER
520 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
522 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
523 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
524 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
525 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
527 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
528 defined CONFIG_AXP818_POWER
529 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
532 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
533 defined CONFIG_AXP818_POWER
534 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
536 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
537 #if !defined(CONFIG_AXP152_POWER)
538 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
540 #ifdef CONFIG_AXP209_POWER
541 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
544 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
545 defined(CONFIG_AXP818_POWER)
546 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
547 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
548 #if !defined CONFIG_AXP809_POWER
549 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
550 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
552 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
553 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
554 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
557 #ifdef CONFIG_AXP818_POWER
558 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
559 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
560 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
563 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
564 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
568 ramsize = sunxi_dram_init();
569 printf(" %d MiB\n", (int)(ramsize >> 20));
574 * Only clock up the CPU to full speed if we are reasonably
575 * assured it's being powered with suitable core voltage
578 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
580 printf("Failed to set core voltage! Can't set CPU frequency\n");
584 #ifdef CONFIG_USB_GADGET
585 int g_dnl_board_usb_cable_connected(void)
587 return sunxi_usb_phy_vbus_detect(0);
591 #ifdef CONFIG_SERIAL_TAG
592 void get_board_serial(struct tag_serialnr *serialnr)
595 unsigned long long serial;
597 serial_string = getenv("serial#");
600 serial = simple_strtoull(serial_string, NULL, 16);
602 serialnr->high = (unsigned int) (serial >> 32);
603 serialnr->low = (unsigned int) (serial & 0xffffffff);
612 * Check the SPL header for the "sunxi" variant. If found: parse values
613 * that might have been passed by the loader ("fel" utility), and update
614 * the environment accordingly.
616 static void parse_spl_header(const uint32_t spl_addr)
618 struct boot_file_head *spl = (void *)(ulong)spl_addr;
619 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
620 return; /* signature mismatch, no usable header */
622 uint8_t spl_header_version = spl->spl_signature[3];
623 if (spl_header_version != SPL_HEADER_VERSION) {
624 printf("sunxi SPL version mismatch: expected %u, got %u\n",
625 SPL_HEADER_VERSION, spl_header_version);
628 if (!spl->fel_script_address)
631 if (spl->fel_uEnv_length != 0) {
633 * data is expected in uEnv.txt compatible format, so "env
634 * import -t" the string(s) at fel_script_address right away.
636 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
637 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
640 /* otherwise assume .scr format (mkimage-type script) */
641 setenv_hex("fel_scriptaddr", spl->fel_script_address);
645 * Note this function gets called multiple times.
646 * It must not make any changes to env variables which already exist.
648 static void setup_environment(const void *fdt)
650 char serial_string[17] = { 0 };
656 ret = sunxi_get_sid(sid);
657 if (ret == 0 && sid[0] != 0) {
659 * The single words 1 - 3 of the SID have quite a few bits
660 * which are the same on many models, so we take a crc32
661 * of all 3 words, to get a more unique value.
663 * Note we only do this on newer SoCs as we cannot change
664 * the algorithm on older SoCs since those have been using
665 * fixed mac-addresses based on only using word 3 for a
666 * long time and changing a fixed mac-address with an
667 * u-boot update is not good.
669 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
670 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
671 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
672 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
675 /* Ensure the NIC specific bytes of the mac are not all 0 */
676 if ((sid[3] & 0xffffff) == 0)
679 for (i = 0; i < 4; i++) {
680 sprintf(ethaddr, "ethernet%d", i);
681 if (!fdt_get_alias(fdt, ethaddr))
685 strcpy(ethaddr, "ethaddr");
687 sprintf(ethaddr, "eth%daddr", i);
692 /* Non OUI / registered MAC address */
693 mac_addr[0] = (i << 4) | 0x02;
694 mac_addr[1] = (sid[0] >> 0) & 0xff;
695 mac_addr[2] = (sid[3] >> 24) & 0xff;
696 mac_addr[3] = (sid[3] >> 16) & 0xff;
697 mac_addr[4] = (sid[3] >> 8) & 0xff;
698 mac_addr[5] = (sid[3] >> 0) & 0xff;
700 eth_setenv_enetaddr(ethaddr, mac_addr);
703 if (!getenv("serial#")) {
704 snprintf(serial_string, sizeof(serial_string),
705 "%08x%08x", sid[0], sid[3]);
707 setenv("serial#", serial_string);
712 int misc_init_r(void)
714 __maybe_unused int ret;
716 setenv("fel_booted", NULL);
717 setenv("fel_scriptaddr", NULL);
718 /* determine if we are running in FEL mode */
719 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
720 setenv("fel_booted", "1");
721 parse_spl_header(SPL_ADDR);
724 setup_environment(gd->fdt_blob);
726 #ifndef CONFIG_MACH_SUN9I
727 ret = sunxi_usb_phy_probe();
731 sunxi_musb_board_init();
736 int ft_board_setup(void *blob, bd_t *bd)
738 int __maybe_unused r;
741 * Call setup_environment again in case the boot fdt has
742 * ethernet aliases the u-boot copy does not have.
744 setup_environment(blob);
746 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
747 r = sunxi_simplefb_setup(blob);