2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some board init for the Allwinner A10-evb board.
11 * SPDX-License-Identifier: GPL-2.0+
16 #ifdef CONFIG_AXP152_POWER
19 #ifdef CONFIG_AXP209_POWER
22 #ifdef CONFIG_AXP221_POWER
25 #include <asm/arch/clock.h>
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/dram.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 /* add board specific code here */
40 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
42 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
43 debug("id_pfr1: 0x%08x\n", id_pfr1);
44 /* Generic Timer Extension available? */
45 if ((id_pfr1 >> 16) & 0xf) {
46 debug("Setting CNTFRQ\n");
47 /* CNTFRQ == 24 MHz */
48 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
56 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
61 #ifdef CONFIG_GENERIC_MMC
62 static void mmc_pinmux_setup(int sdc)
68 /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
69 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
70 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
71 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
72 sunxi_gpio_set_drv(pin, 2);
77 /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
78 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
79 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1);
80 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
81 sunxi_gpio_set_drv(pin, 2);
86 /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
87 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
88 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
89 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
90 sunxi_gpio_set_drv(pin, 2);
95 /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
96 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
97 sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
98 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
99 sunxi_gpio_set_drv(pin, 2);
104 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
109 int board_mmc_init(bd_t *bis)
111 __maybe_unused struct mmc *mmc0, *mmc1;
112 __maybe_unused char buf[512];
114 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
115 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
119 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
120 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
121 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
126 #if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
128 * Both mmc0 and mmc2 are bootable, figure out where we're booting
129 * from. Try mmc0 first, just like the brom does.
131 if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 &&
132 mmc0->block_dev.block_read(0, 16, 1, buf) == 1) {
134 if (strcmp(&buf[4], "eGON.BT0") == 0)
138 /* no bootable card in mmc0, so we must be booting from mmc2, swap */
139 mmc0->block_dev.dev = 1;
140 mmc1->block_dev.dev = 0;
147 void i2c_init_board(void)
149 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
150 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
151 clock_twi_onoff(0, 1);
154 #ifdef CONFIG_SPL_BUILD
155 void sunxi_board_init(void)
157 int power_failed = 0;
158 unsigned long ramsize;
160 #ifdef CONFIG_AXP152_POWER
161 power_failed = axp152_init();
162 power_failed |= axp152_set_dcdc2(1400);
163 power_failed |= axp152_set_dcdc3(1500);
164 power_failed |= axp152_set_dcdc4(1250);
165 power_failed |= axp152_set_ldo2(3000);
167 #ifdef CONFIG_AXP209_POWER
168 power_failed |= axp209_init();
169 power_failed |= axp209_set_dcdc2(1400);
170 power_failed |= axp209_set_dcdc3(1250);
171 power_failed |= axp209_set_ldo2(3000);
172 power_failed |= axp209_set_ldo3(2800);
173 power_failed |= axp209_set_ldo4(2800);
175 #ifdef CONFIG_AXP221_POWER
176 power_failed = axp221_init();
177 power_failed |= axp221_set_dcdc1(3000);
178 power_failed |= axp221_set_dcdc2(1200);
179 power_failed |= axp221_set_dcdc3(1200);
180 power_failed |= axp221_set_dcdc4(1200);
181 power_failed |= axp221_set_dcdc5(1500);
182 #if CONFIG_AXP221_DLDO1_VOLT != -1
183 power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
185 #if CONFIG_AXP221_DLDO4_VOLT != -1
186 power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
188 #if CONFIG_AXP221_ALDO1_VOLT != -1
189 power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
191 #if CONFIG_AXP221_ALDO2_VOLT != -1
192 power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
194 #if CONFIG_AXP221_ALDO3_VOLT != -1
195 power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
200 ramsize = sunxi_dram_init();
201 printf(" %lu MiB\n", ramsize >> 20);
206 * Only clock up the CPU to full speed if we are reasonably
207 * assured it's being powered with suitable core voltage
210 clock_set_pll1(CONFIG_CLK_FULL_SPEED);
212 printf("Failed to set core voltage! Can't set CPU frequency\n");
216 #ifdef CONFIG_MISC_INIT_R
217 int misc_init_r(void)
219 if (!getenv("ethaddr")) {
220 uint32_t reg_val = readl(SUNXI_SID_BASE);
225 mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
226 mac_addr[1] = (reg_val >> 0) & 0xff;
227 reg_val = readl(SUNXI_SID_BASE + 0x0c);
228 mac_addr[2] = (reg_val >> 24) & 0xff;
229 mac_addr[3] = (reg_val >> 16) & 0xff;
230 mac_addr[4] = (reg_val >> 8) & 0xff;
231 mac_addr[5] = (reg_val >> 0) & 0xff;
233 eth_setenv_enetaddr("ethaddr", mac_addr);