2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some board init for the Allwinner A10-evb board.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/display.h>
20 #include <asm/arch/dram.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc.h>
23 #include <asm/arch/spl.h>
24 #include <asm/arch/usb_phy.h>
26 #include <asm/armv7.h>
31 #include <environment.h>
32 #include <linux/libfdt.h>
37 #include <asm/setup.h>
39 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
40 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
41 int soft_i2c_gpio_sda;
42 int soft_i2c_gpio_scl;
44 static int soft_i2c_board_init(void)
48 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
49 if (soft_i2c_gpio_sda < 0) {
50 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
51 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
52 return soft_i2c_gpio_sda;
54 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
56 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
57 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
61 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
62 if (soft_i2c_gpio_scl < 0) {
63 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
64 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
65 return soft_i2c_gpio_scl;
67 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
69 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
70 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
77 static int soft_i2c_board_init(void) { return 0; }
80 DECLARE_GLOBAL_DATA_PTR;
82 void i2c_init_board(void)
84 #ifdef CONFIG_I2C0_ENABLE
85 #if defined(CONFIG_MACH_SUN4I) || \
86 defined(CONFIG_MACH_SUN5I) || \
87 defined(CONFIG_MACH_SUN7I) || \
88 defined(CONFIG_MACH_SUN8I_R40)
89 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
91 clock_twi_onoff(0, 1);
92 #elif defined(CONFIG_MACH_SUN6I)
93 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
94 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
95 clock_twi_onoff(0, 1);
96 #elif defined(CONFIG_MACH_SUN8I)
97 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
99 clock_twi_onoff(0, 1);
103 #ifdef CONFIG_I2C1_ENABLE
104 #if defined(CONFIG_MACH_SUN4I) || \
105 defined(CONFIG_MACH_SUN7I) || \
106 defined(CONFIG_MACH_SUN8I_R40)
107 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
109 clock_twi_onoff(1, 1);
110 #elif defined(CONFIG_MACH_SUN5I)
111 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
112 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
113 clock_twi_onoff(1, 1);
114 #elif defined(CONFIG_MACH_SUN6I)
115 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
117 clock_twi_onoff(1, 1);
118 #elif defined(CONFIG_MACH_SUN8I)
119 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
120 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
121 clock_twi_onoff(1, 1);
125 #ifdef CONFIG_I2C2_ENABLE
126 #if defined(CONFIG_MACH_SUN4I) || \
127 defined(CONFIG_MACH_SUN7I) || \
128 defined(CONFIG_MACH_SUN8I_R40)
129 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
131 clock_twi_onoff(2, 1);
132 #elif defined(CONFIG_MACH_SUN5I)
133 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
134 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
135 clock_twi_onoff(2, 1);
136 #elif defined(CONFIG_MACH_SUN6I)
137 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
139 clock_twi_onoff(2, 1);
140 #elif defined(CONFIG_MACH_SUN8I)
141 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
142 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
143 clock_twi_onoff(2, 1);
147 #ifdef CONFIG_I2C3_ENABLE
148 #if defined(CONFIG_MACH_SUN6I)
149 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
150 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
151 clock_twi_onoff(3, 1);
152 #elif defined(CONFIG_MACH_SUN7I) || \
153 defined(CONFIG_MACH_SUN8I_R40)
154 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
155 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
156 clock_twi_onoff(3, 1);
160 #ifdef CONFIG_I2C4_ENABLE
161 #if defined(CONFIG_MACH_SUN7I) || \
162 defined(CONFIG_MACH_SUN8I_R40)
163 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
164 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
165 clock_twi_onoff(4, 1);
169 #ifdef CONFIG_R_I2C_ENABLE
170 clock_twi_onoff(5, 1);
171 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
172 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
176 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
177 enum env_location env_get_location(enum env_operation op, int prio)
192 /* add board specific code here */
195 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
197 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
200 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
201 debug("id_pfr1: 0x%08x\n", id_pfr1);
202 /* Generic Timer Extension available? */
203 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
206 debug("Setting CNTFRQ\n");
209 * CNTFRQ is a secure register, so we will crash if we try to
210 * write this from the non-secure world (read is OK, though).
211 * In case some bootcode has already set the correct value,
212 * we avoid the risk of writing to it.
214 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
215 if (freq != COUNTER_FREQUENCY) {
216 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
217 freq, COUNTER_FREQUENCY);
218 #ifdef CONFIG_NON_SECURE
219 printf("arch timer frequency is wrong, but cannot adjust it\n");
221 asm volatile("mcr p15, 0, %0, c14, c0, 0"
222 : : "r"(COUNTER_FREQUENCY));
226 #endif /* !CONFIG_ARM64 */
228 ret = axp_gpio_init();
232 #ifdef CONFIG_SATAPWR
233 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
234 gpio_request(satapwr_pin, "satapwr");
235 gpio_direction_output(satapwr_pin, 1);
236 /* Give attached sata device time to power-up to avoid link timeouts */
240 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
241 gpio_request(macpwr_pin, "macpwr");
242 gpio_direction_output(macpwr_pin, 1);
247 * Temporary workaround for enabling I2C clocks until proper sunxi DM
248 * clk, reset and pinctrl drivers land.
253 /* Uses dm gpio code so do this here and not in i2c_init_board() */
254 return soft_i2c_board_init();
259 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
264 #if defined(CONFIG_NAND_SUNXI)
265 static void nand_pinmux_setup(void)
269 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
270 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
272 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
273 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
274 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
276 /* sun4i / sun7i do have a PC23, but it is not used for nand,
277 * only sun7i has a PC24 */
278 #ifdef CONFIG_MACH_SUN7I
279 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
283 static void nand_clock_setup(void)
285 struct sunxi_ccm_reg *const ccm =
286 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
288 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
289 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
290 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
291 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
293 #ifdef CONFIG_MACH_SUN9I
294 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
296 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
298 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
301 void board_nand_init(void)
305 #ifndef CONFIG_SPL_BUILD
312 static void mmc_pinmux_setup(int sdc)
315 __maybe_unused int pins;
320 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
321 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
322 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
323 sunxi_gpio_set_drv(pin, 2);
328 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
330 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
331 defined(CONFIG_MACH_SUN8I_R40)
332 if (pins == SUNXI_GPIO_H) {
333 /* SDC1: PH22-PH-27 */
334 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
335 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
336 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
337 sunxi_gpio_set_drv(pin, 2);
341 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
342 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
343 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
344 sunxi_gpio_set_drv(pin, 2);
347 #elif defined(CONFIG_MACH_SUN5I)
349 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
350 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
351 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
352 sunxi_gpio_set_drv(pin, 2);
354 #elif defined(CONFIG_MACH_SUN6I)
356 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
357 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
358 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
359 sunxi_gpio_set_drv(pin, 2);
361 #elif defined(CONFIG_MACH_SUN8I)
362 if (pins == SUNXI_GPIO_D) {
364 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
365 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
366 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
367 sunxi_gpio_set_drv(pin, 2);
371 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
372 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
373 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
374 sunxi_gpio_set_drv(pin, 2);
381 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
383 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
385 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
386 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
387 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
388 sunxi_gpio_set_drv(pin, 2);
390 #elif defined(CONFIG_MACH_SUN5I)
391 if (pins == SUNXI_GPIO_E) {
393 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
394 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
395 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
396 sunxi_gpio_set_drv(pin, 2);
400 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
401 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
402 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
403 sunxi_gpio_set_drv(pin, 2);
406 #elif defined(CONFIG_MACH_SUN6I)
407 if (pins == SUNXI_GPIO_A) {
409 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
410 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
411 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
412 sunxi_gpio_set_drv(pin, 2);
415 /* SDC2: PC6-PC15, PC24 */
416 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
417 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
418 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
419 sunxi_gpio_set_drv(pin, 2);
422 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
423 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
424 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
426 #elif defined(CONFIG_MACH_SUN8I_R40)
427 /* SDC2: PC6-PC15, PC24 */
428 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
429 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
430 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
431 sunxi_gpio_set_drv(pin, 2);
434 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
435 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
436 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
437 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
438 /* SDC2: PC5-PC6, PC8-PC16 */
439 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
440 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
441 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
442 sunxi_gpio_set_drv(pin, 2);
445 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
446 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
447 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
448 sunxi_gpio_set_drv(pin, 2);
450 #elif defined(CONFIG_MACH_SUN9I)
452 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
453 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
454 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
455 sunxi_gpio_set_drv(pin, 2);
461 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
463 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
464 defined(CONFIG_MACH_SUN8I_R40)
466 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
467 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
468 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
469 sunxi_gpio_set_drv(pin, 2);
471 #elif defined(CONFIG_MACH_SUN6I)
472 if (pins == SUNXI_GPIO_A) {
474 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
475 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
476 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
477 sunxi_gpio_set_drv(pin, 2);
480 /* SDC3: PC6-PC15, PC24 */
481 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
482 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
483 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
484 sunxi_gpio_set_drv(pin, 2);
487 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
488 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
489 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
495 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
500 int board_mmc_init(bd_t *bis)
502 __maybe_unused struct mmc *mmc0, *mmc1;
503 __maybe_unused char buf[512];
505 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
506 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
510 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
511 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
512 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
521 #ifdef CONFIG_SPL_BUILD
522 void sunxi_board_init(void)
524 int power_failed = 0;
526 #ifdef CONFIG_SY8106A_POWER
527 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
530 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
531 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
532 defined CONFIG_AXP818_POWER
533 power_failed = axp_init();
535 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
536 defined CONFIG_AXP818_POWER
537 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
539 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
540 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
541 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
542 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
544 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
545 defined CONFIG_AXP818_POWER
546 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
549 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
550 defined CONFIG_AXP818_POWER
551 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
553 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
554 #if !defined(CONFIG_AXP152_POWER)
555 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
557 #ifdef CONFIG_AXP209_POWER
558 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
561 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
562 defined(CONFIG_AXP818_POWER)
563 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
564 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
565 #if !defined CONFIG_AXP809_POWER
566 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
567 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
569 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
570 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
571 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
574 #ifdef CONFIG_AXP818_POWER
575 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
576 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
577 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
580 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
581 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
585 gd->ram_size = sunxi_dram_init();
586 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
591 * Only clock up the CPU to full speed if we are reasonably
592 * assured it's being powered with suitable core voltage
595 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
597 printf("Failed to set core voltage! Can't set CPU frequency\n");
601 #ifdef CONFIG_USB_GADGET
602 int g_dnl_board_usb_cable_connected(void)
604 return sunxi_usb_phy_vbus_detect(0);
608 #ifdef CONFIG_SERIAL_TAG
609 void get_board_serial(struct tag_serialnr *serialnr)
612 unsigned long long serial;
614 serial_string = env_get("serial#");
617 serial = simple_strtoull(serial_string, NULL, 16);
619 serialnr->high = (unsigned int) (serial >> 32);
620 serialnr->low = (unsigned int) (serial & 0xffffffff);
629 * Check the SPL header for the "sunxi" variant. If found: parse values
630 * that might have been passed by the loader ("fel" utility), and update
631 * the environment accordingly.
633 static void parse_spl_header(const uint32_t spl_addr)
635 struct boot_file_head *spl = (void *)(ulong)spl_addr;
636 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
637 return; /* signature mismatch, no usable header */
639 uint8_t spl_header_version = spl->spl_signature[3];
640 if (spl_header_version != SPL_HEADER_VERSION) {
641 printf("sunxi SPL version mismatch: expected %u, got %u\n",
642 SPL_HEADER_VERSION, spl_header_version);
645 if (!spl->fel_script_address)
648 if (spl->fel_uEnv_length != 0) {
650 * data is expected in uEnv.txt compatible format, so "env
651 * import -t" the string(s) at fel_script_address right away.
653 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
654 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
657 /* otherwise assume .scr format (mkimage-type script) */
658 env_set_hex("fel_scriptaddr", spl->fel_script_address);
662 * Note this function gets called multiple times.
663 * It must not make any changes to env variables which already exist.
665 static void setup_environment(const void *fdt)
667 char serial_string[17] = { 0 };
673 ret = sunxi_get_sid(sid);
674 if (ret == 0 && sid[0] != 0) {
676 * The single words 1 - 3 of the SID have quite a few bits
677 * which are the same on many models, so we take a crc32
678 * of all 3 words, to get a more unique value.
680 * Note we only do this on newer SoCs as we cannot change
681 * the algorithm on older SoCs since those have been using
682 * fixed mac-addresses based on only using word 3 for a
683 * long time and changing a fixed mac-address with an
684 * u-boot update is not good.
686 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
687 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
688 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
689 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
692 /* Ensure the NIC specific bytes of the mac are not all 0 */
693 if ((sid[3] & 0xffffff) == 0)
696 for (i = 0; i < 4; i++) {
697 sprintf(ethaddr, "ethernet%d", i);
698 if (!fdt_get_alias(fdt, ethaddr))
702 strcpy(ethaddr, "ethaddr");
704 sprintf(ethaddr, "eth%daddr", i);
706 if (env_get(ethaddr))
709 /* Non OUI / registered MAC address */
710 mac_addr[0] = (i << 4) | 0x02;
711 mac_addr[1] = (sid[0] >> 0) & 0xff;
712 mac_addr[2] = (sid[3] >> 24) & 0xff;
713 mac_addr[3] = (sid[3] >> 16) & 0xff;
714 mac_addr[4] = (sid[3] >> 8) & 0xff;
715 mac_addr[5] = (sid[3] >> 0) & 0xff;
717 eth_env_set_enetaddr(ethaddr, mac_addr);
720 if (!env_get("serial#")) {
721 snprintf(serial_string, sizeof(serial_string),
722 "%08x%08x", sid[0], sid[3]);
724 env_set("serial#", serial_string);
729 int misc_init_r(void)
731 __maybe_unused int ret;
734 env_set("fel_booted", NULL);
735 env_set("fel_scriptaddr", NULL);
736 env_set("mmc_bootdev", NULL);
738 boot = sunxi_get_boot_device();
739 /* determine if we are running in FEL mode */
740 if (boot == BOOT_DEVICE_BOARD) {
741 env_set("fel_booted", "1");
742 parse_spl_header(SPL_ADDR);
743 /* or if we booted from MMC, and which one */
744 } else if (boot == BOOT_DEVICE_MMC1) {
745 env_set("mmc_bootdev", "0");
746 } else if (boot == BOOT_DEVICE_MMC2) {
747 env_set("mmc_bootdev", "1");
750 setup_environment(gd->fdt_blob);
752 #ifndef CONFIG_MACH_SUN9I
753 ret = sunxi_usb_phy_probe();
758 #ifdef CONFIG_USB_ETHER
765 int ft_board_setup(void *blob, bd_t *bd)
767 int __maybe_unused r;
770 * Call setup_environment again in case the boot fdt has
771 * ethernet aliases the u-boot copy does not have.
773 setup_environment(blob);
775 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
776 r = sunxi_simplefb_setup(blob);
783 #ifdef CONFIG_SPL_LOAD_FIT
784 int board_fit_config_name_match(const char *name)
786 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
787 const char *cmp_str = (void *)(ulong)SPL_ADDR;
789 /* Check if there is a DT name stored in the SPL header and use that. */
790 if (spl->dt_name_offset) {
791 cmp_str += spl->dt_name_offset;
793 #ifdef CONFIG_DEFAULT_DEVICE_TREE
794 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
800 /* Differentiate the two Pine64 board DTs by their DRAM size. */
801 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
802 if ((gd->ram_size > 512 * 1024 * 1024))
803 return !strstr(name, "plus");
805 return !!strstr(name, "plus");
807 return strcmp(name, cmp_str);