2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some board init for the Allwinner A10-evb board.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/display.h>
20 #include <asm/arch/dram.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc.h>
23 #include <asm/arch/spl.h>
24 #include <asm/arch/usb_phy.h>
26 #include <asm/armv7.h>
31 #include <environment.h>
37 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
38 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
39 int soft_i2c_gpio_sda;
40 int soft_i2c_gpio_scl;
42 static int soft_i2c_board_init(void)
46 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
47 if (soft_i2c_gpio_sda < 0) {
48 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
49 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
50 return soft_i2c_gpio_sda;
52 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
54 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
59 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
60 if (soft_i2c_gpio_scl < 0) {
61 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
62 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
63 return soft_i2c_gpio_scl;
65 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
67 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
75 static int soft_i2c_board_init(void) { return 0; }
78 DECLARE_GLOBAL_DATA_PTR;
80 /* add board specific code here */
83 __maybe_unused int id_pfr1, ret, satapwr_pin;
85 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
88 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
89 debug("id_pfr1: 0x%08x\n", id_pfr1);
90 /* Generic Timer Extension available? */
91 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
94 debug("Setting CNTFRQ\n");
97 * CNTFRQ is a secure register, so we will crash if we try to
98 * write this from the non-secure world (read is OK, though).
99 * In case some bootcode has already set the correct value,
100 * we avoid the risk of writing to it.
102 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
103 if (freq != COUNTER_FREQUENCY) {
104 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
105 freq, COUNTER_FREQUENCY);
106 #ifdef CONFIG_NON_SECURE
107 printf("arch timer frequency is wrong, but cannot adjust it\n");
109 asm volatile("mcr p15, 0, %0, c14, c0, 0"
110 : : "r"(COUNTER_FREQUENCY));
114 #endif /* !CONFIG_ARM64 */
116 ret = axp_gpio_init();
120 #ifdef CONFIG_SATAPWR
121 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
122 gpio_request(satapwr_pin, "satapwr");
123 gpio_direction_output(satapwr_pin, 1);
126 gpio_request(CONFIG_MACPWR, "macpwr");
127 gpio_direction_output(CONFIG_MACPWR, 1);
130 /* Uses dm gpio code so do this here and not in i2c_init_board() */
131 return soft_i2c_board_init();
136 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
141 #if defined(CONFIG_NAND_SUNXI)
142 static void nand_pinmux_setup(void)
146 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
147 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
149 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
150 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
151 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
153 /* sun4i / sun7i do have a PC23, but it is not used for nand,
154 * only sun7i has a PC24 */
155 #ifdef CONFIG_MACH_SUN7I
156 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
160 static void nand_clock_setup(void)
162 struct sunxi_ccm_reg *const ccm =
163 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
165 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
166 #ifdef CONFIG_MACH_SUN9I
167 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
169 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
171 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
174 void board_nand_init(void)
178 #ifndef CONFIG_SPL_BUILD
184 #ifdef CONFIG_GENERIC_MMC
185 static void mmc_pinmux_setup(int sdc)
188 __maybe_unused int pins;
193 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
194 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
195 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
196 sunxi_gpio_set_drv(pin, 2);
201 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
203 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
204 if (pins == SUNXI_GPIO_H) {
205 /* SDC1: PH22-PH-27 */
206 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
207 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
208 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
209 sunxi_gpio_set_drv(pin, 2);
213 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
214 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
215 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
216 sunxi_gpio_set_drv(pin, 2);
219 #elif defined(CONFIG_MACH_SUN5I)
221 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
222 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
223 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
224 sunxi_gpio_set_drv(pin, 2);
226 #elif defined(CONFIG_MACH_SUN6I)
228 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
229 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
230 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
231 sunxi_gpio_set_drv(pin, 2);
233 #elif defined(CONFIG_MACH_SUN8I)
234 if (pins == SUNXI_GPIO_D) {
236 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
237 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
238 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
239 sunxi_gpio_set_drv(pin, 2);
243 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
244 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
245 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
246 sunxi_gpio_set_drv(pin, 2);
253 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
255 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
257 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
258 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
259 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
260 sunxi_gpio_set_drv(pin, 2);
262 #elif defined(CONFIG_MACH_SUN5I)
263 if (pins == SUNXI_GPIO_E) {
265 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
266 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
267 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
268 sunxi_gpio_set_drv(pin, 2);
272 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
273 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
274 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
275 sunxi_gpio_set_drv(pin, 2);
278 #elif defined(CONFIG_MACH_SUN6I)
279 if (pins == SUNXI_GPIO_A) {
281 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
282 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
283 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
284 sunxi_gpio_set_drv(pin, 2);
287 /* SDC2: PC6-PC15, PC24 */
288 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
289 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
290 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
291 sunxi_gpio_set_drv(pin, 2);
294 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
295 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
296 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
298 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
299 /* SDC2: PC5-PC6, PC8-PC16 */
300 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
301 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
302 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
303 sunxi_gpio_set_drv(pin, 2);
306 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
307 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
308 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
309 sunxi_gpio_set_drv(pin, 2);
311 #elif defined(CONFIG_MACH_SUN9I)
313 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
314 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
315 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
316 sunxi_gpio_set_drv(pin, 2);
322 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
324 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
326 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
327 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
328 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
329 sunxi_gpio_set_drv(pin, 2);
331 #elif defined(CONFIG_MACH_SUN6I)
332 if (pins == SUNXI_GPIO_A) {
334 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
335 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
336 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
337 sunxi_gpio_set_drv(pin, 2);
340 /* SDC3: PC6-PC15, PC24 */
341 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
342 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
343 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
344 sunxi_gpio_set_drv(pin, 2);
347 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
348 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
349 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
355 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
360 int board_mmc_init(bd_t *bis)
362 __maybe_unused struct mmc *mmc0, *mmc1;
363 __maybe_unused char buf[512];
365 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
366 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
370 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
371 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
372 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
377 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
379 * On systems with an emmc (mmc2), figure out if we are booting from
380 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc.
381 * are searched there first. Note we only do this for u-boot proper,
382 * not for the SPL, see spl_boot_device().
384 if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) {
385 /* Booting from emmc / mmc2, swap */
386 mmc0->block_dev.devnum = 1;
387 mmc1->block_dev.devnum = 0;
395 void i2c_init_board(void)
397 #ifdef CONFIG_I2C0_ENABLE
398 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
399 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
400 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
401 clock_twi_onoff(0, 1);
402 #elif defined(CONFIG_MACH_SUN6I)
403 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
404 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
405 clock_twi_onoff(0, 1);
406 #elif defined(CONFIG_MACH_SUN8I)
407 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
408 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
409 clock_twi_onoff(0, 1);
413 #ifdef CONFIG_I2C1_ENABLE
414 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
415 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
416 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
417 clock_twi_onoff(1, 1);
418 #elif defined(CONFIG_MACH_SUN5I)
419 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
420 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
421 clock_twi_onoff(1, 1);
422 #elif defined(CONFIG_MACH_SUN6I)
423 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
424 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
425 clock_twi_onoff(1, 1);
426 #elif defined(CONFIG_MACH_SUN8I)
427 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
428 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
429 clock_twi_onoff(1, 1);
433 #ifdef CONFIG_I2C2_ENABLE
434 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
435 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
436 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
437 clock_twi_onoff(2, 1);
438 #elif defined(CONFIG_MACH_SUN5I)
439 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
440 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
441 clock_twi_onoff(2, 1);
442 #elif defined(CONFIG_MACH_SUN6I)
443 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
444 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
445 clock_twi_onoff(2, 1);
446 #elif defined(CONFIG_MACH_SUN8I)
447 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
448 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
449 clock_twi_onoff(2, 1);
453 #ifdef CONFIG_I2C3_ENABLE
454 #if defined(CONFIG_MACH_SUN6I)
455 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
456 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
457 clock_twi_onoff(3, 1);
458 #elif defined(CONFIG_MACH_SUN7I)
459 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
460 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
461 clock_twi_onoff(3, 1);
465 #ifdef CONFIG_I2C4_ENABLE
466 #if defined(CONFIG_MACH_SUN7I)
467 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
468 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
469 clock_twi_onoff(4, 1);
473 #ifdef CONFIG_R_I2C_ENABLE
474 clock_twi_onoff(5, 1);
475 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
476 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
480 #ifdef CONFIG_SPL_BUILD
481 void sunxi_board_init(void)
483 int power_failed = 0;
484 unsigned long ramsize;
486 #ifdef CONFIG_SY8106A_POWER
487 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
490 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
491 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
492 defined CONFIG_AXP818_POWER
493 power_failed = axp_init();
495 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
496 defined CONFIG_AXP818_POWER
497 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
499 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
500 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
501 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
502 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
504 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
505 defined CONFIG_AXP818_POWER
506 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
509 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
510 defined CONFIG_AXP818_POWER
511 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
513 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
514 #if !defined(CONFIG_AXP152_POWER)
515 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
517 #ifdef CONFIG_AXP209_POWER
518 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
521 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
522 defined(CONFIG_AXP818_POWER)
523 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
524 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
525 #if !defined CONFIG_AXP809_POWER
526 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
527 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
529 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
530 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
531 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
534 #ifdef CONFIG_AXP818_POWER
535 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
536 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
537 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
540 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
541 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
545 ramsize = sunxi_dram_init();
546 printf(" %d MiB\n", (int)(ramsize >> 20));
551 * Only clock up the CPU to full speed if we are reasonably
552 * assured it's being powered with suitable core voltage
555 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
557 printf("Failed to set core voltage! Can't set CPU frequency\n");
561 #ifdef CONFIG_USB_GADGET
562 int g_dnl_board_usb_cable_connected(void)
564 return sunxi_usb_phy_vbus_detect(0);
568 #ifdef CONFIG_SERIAL_TAG
569 void get_board_serial(struct tag_serialnr *serialnr)
572 unsigned long long serial;
574 serial_string = getenv("serial#");
577 serial = simple_strtoull(serial_string, NULL, 16);
579 serialnr->high = (unsigned int) (serial >> 32);
580 serialnr->low = (unsigned int) (serial & 0xffffffff);
589 * Check the SPL header for the "sunxi" variant. If found: parse values
590 * that might have been passed by the loader ("fel" utility), and update
591 * the environment accordingly.
593 static void parse_spl_header(const uint32_t spl_addr)
595 struct boot_file_head *spl = (void *)(ulong)spl_addr;
596 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
597 return; /* signature mismatch, no usable header */
599 uint8_t spl_header_version = spl->spl_signature[3];
600 if (spl_header_version != SPL_HEADER_VERSION) {
601 printf("sunxi SPL version mismatch: expected %u, got %u\n",
602 SPL_HEADER_VERSION, spl_header_version);
605 if (!spl->fel_script_address)
608 if (spl->fel_uEnv_length != 0) {
610 * data is expected in uEnv.txt compatible format, so "env
611 * import -t" the string(s) at fel_script_address right away.
613 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
614 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
617 /* otherwise assume .scr format (mkimage-type script) */
618 setenv_hex("fel_scriptaddr", spl->fel_script_address);
622 * Note this function gets called multiple times.
623 * It must not make any changes to env variables which already exist.
625 static void setup_environment(const void *fdt)
627 char serial_string[17] = { 0 };
633 ret = sunxi_get_sid(sid);
634 if (ret == 0 && sid[0] != 0) {
636 * The single words 1 - 3 of the SID have quite a few bits
637 * which are the same on many models, so we take a crc32
638 * of all 3 words, to get a more unique value.
640 * Note we only do this on newer SoCs as we cannot change
641 * the algorithm on older SoCs since those have been using
642 * fixed mac-addresses based on only using word 3 for a
643 * long time and changing a fixed mac-address with an
644 * u-boot update is not good.
646 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
647 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
648 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
649 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
652 /* Ensure the NIC specific bytes of the mac are not all 0 */
653 if ((sid[3] & 0xffffff) == 0)
656 for (i = 0; i < 4; i++) {
657 sprintf(ethaddr, "ethernet%d", i);
658 if (!fdt_get_alias(fdt, ethaddr))
662 strcpy(ethaddr, "ethaddr");
664 sprintf(ethaddr, "eth%daddr", i);
669 /* Non OUI / registered MAC address */
670 mac_addr[0] = (i << 4) | 0x02;
671 mac_addr[1] = (sid[0] >> 0) & 0xff;
672 mac_addr[2] = (sid[3] >> 24) & 0xff;
673 mac_addr[3] = (sid[3] >> 16) & 0xff;
674 mac_addr[4] = (sid[3] >> 8) & 0xff;
675 mac_addr[5] = (sid[3] >> 0) & 0xff;
677 eth_setenv_enetaddr(ethaddr, mac_addr);
680 if (!getenv("serial#")) {
681 snprintf(serial_string, sizeof(serial_string),
682 "%08x%08x", sid[0], sid[3]);
684 setenv("serial#", serial_string);
689 int misc_init_r(void)
691 __maybe_unused int ret;
693 setenv("fel_booted", NULL);
694 setenv("fel_scriptaddr", NULL);
695 /* determine if we are running in FEL mode */
696 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
697 setenv("fel_booted", "1");
698 parse_spl_header(SPL_ADDR);
701 setup_environment(gd->fdt_blob);
703 #ifndef CONFIG_MACH_SUN9I
704 ret = sunxi_usb_phy_probe();
708 sunxi_musb_board_init();
713 int ft_board_setup(void *blob, bd_t *bd)
715 int __maybe_unused r;
718 * Call setup_environment again in case the boot fdt has
719 * ethernet aliases the u-boot copy does not have.
721 setup_environment(blob);
723 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
724 r = sunxi_simplefb_setup(blob);