2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
7 * -- Some bits of code used from rrload's head_OMAP1510.s --
8 * Copyright (C) 2002 RidgeRun, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if defined(CONFIG_OMAP1510)
33 #include <./configs/omap1510.h>
36 #define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
40 .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
46 * Configure 1510 pins functions to match our board.
48 ldr r0, REG_PULL_DWN_CTRL_0
49 ldr r1, VAL_PULL_DWN_CTRL_0
51 ldr r0, REG_PULL_DWN_CTRL_1
52 ldr r1, VAL_PULL_DWN_CTRL_1
54 ldr r0, REG_PULL_DWN_CTRL_2
55 ldr r1, VAL_PULL_DWN_CTRL_2
57 ldr r0, REG_PULL_DWN_CTRL_3
58 ldr r1, VAL_PULL_DWN_CTRL_3
60 ldr r0, REG_FUNC_MUX_CTRL_4
61 ldr r1, VAL_FUNC_MUX_CTRL_4
63 ldr r0, REG_FUNC_MUX_CTRL_5
64 ldr r1, VAL_FUNC_MUX_CTRL_5
66 ldr r0, REG_FUNC_MUX_CTRL_6
67 ldr r1, VAL_FUNC_MUX_CTRL_6
69 ldr r0, REG_FUNC_MUX_CTRL_7
70 ldr r1, VAL_FUNC_MUX_CTRL_7
72 ldr r0, REG_FUNC_MUX_CTRL_8
73 ldr r1, VAL_FUNC_MUX_CTRL_8
75 ldr r0, REG_FUNC_MUX_CTRL_9
76 ldr r1, VAL_FUNC_MUX_CTRL_9
78 ldr r0, REG_FUNC_MUX_CTRL_A
79 ldr r1, VAL_FUNC_MUX_CTRL_A
81 ldr r0, REG_FUNC_MUX_CTRL_B
82 ldr r1, VAL_FUNC_MUX_CTRL_B
84 ldr r0, REG_FUNC_MUX_CTRL_C
85 ldr r1, VAL_FUNC_MUX_CTRL_C
87 ldr r0, REG_FUNC_MUX_CTRL_D
88 ldr r1, VAL_FUNC_MUX_CTRL_D
90 ldr r0, REG_VOLTAGE_CTRL_0
91 ldr r1, VAL_VOLTAGE_CTRL_0
93 ldr r0, REG_TEST_DBG_CTRL_0
94 ldr r1, VAL_TEST_DBG_CTRL_0
96 ldr r0, REG_MOD_CONF_CTRL_0
97 ldr r1, VAL_MOD_CONF_CTRL_0
100 /* Move to 1510 mode */
101 ldr r0, REG_COMP_MODE_CTRL_0
102 ldr r1, VAL_COMP_MODE_CTRL_0
105 /* Set up Traffic Ctlr*/
106 ldr r0, REG_TC_IMIF_PRIO
109 ldr r0, REG_TC_EMIFS_PRIO
111 ldr r0, REG_TC_EMIFF_PRIO
114 ldr r0, REG_TC_EMIFS_CONFIG
116 bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */
117 bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */
118 str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */
120 ldr r0, _GPIO_PIN_CONTROL_REG
122 orr r1, r1, #0x0001 /* M_PCM_SYNC */
123 orr r1, r1, #0x4000 /* IPC_ACTIVE */
126 ldr r0, _GPIO_DIR_CONTROL_REG
128 bic r1, r1, #0x0001 /* M_PCM_SYNC */
129 bic r1, r1, #0x4000 /* IPC_ACTIVE */
132 ldr r0, _GPIO_DATA_OUTPUT_REG
134 bic r1, r1, #0x0001 /* M_PCM_SYNC */
135 orr r1, r1, #0x4000 /* IPC_ACTIVE */
138 /* Setup some clock domains */
139 ldr r1, =OMAP1510_CLKS
140 ldr r0, REG_ARM_IDLECT2
141 strh r1, [r0] /* CLKM, Clock domain control. */
143 mov r1, #0x01 /* PER_EN bit */
144 ldr r0, REG_ARM_RSTCT2
145 strh r1, [r0] /* CLKM; Peripheral reset. */
147 /* Set CLKM to Sync-Scalable */
148 /* I supposidly need to enable the dsp clock before switching */
150 ldr r0, REG_ARM_SYSST
154 subs r0, r0, #0x1 /* wait for any bubbles to finish */
157 ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
158 ldr r0, REG_ARM_CKCTL
162 ldr r1, VAL_DPLL1_CTL
163 ldr r0, REG_DPLL1_CTL
165 ands r1, r1, #0x10 /* Check if PLL is enabled. */
166 beq lock_end /* Do not look for lock if BYPASS selected */
169 ands r1, r1, #0x01 /* Check the LOCK bit. */
170 beq 2b /* ...loop until bit goes hi. */
173 /* Set memory timings corresponding to the new clock speed */
175 /* Check execution location to determine current execution location
176 * and branch to appropriate initialization code.
178 mov r0, #0x10000000 /* Load physical SDRAM base. */
179 mov r1, pc /* Get current execution location. */
180 cmp r1, r0 /* Compare. */
181 bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
184 * Delay for SDRAM initialization.
186 mov r3, #0x1800 /* value should be checked */
188 subs r3, r3, #0x1 /* Decrement count */
192 * Set SDRAM control values. Disable refresh before MRS command.
194 ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */
195 bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
196 orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */
197 orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */
198 ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
199 str r3, [r2] /* Store the passed value with AR disabled. */
201 ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */
202 ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */
203 str r1, [r2] /* Store the passed value.*/
205 ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
206 str r0, [r2] /* Store the passed value. */
209 * Delay for SDRAM initialization.
213 subs r3, r3, #1 /* Decrement count. */
219 ldr r1, VAL_TC_EMIFS_CS0_CONFIG
220 ldr r0, REG_TC_EMIFS_CS0_CONFIG
221 str r1, [r0] /* Chip Select 0 */
222 ldr r1, VAL_TC_EMIFS_CS1_CONFIG
223 ldr r0, REG_TC_EMIFS_CS1_CONFIG
224 str r1, [r0] /* Chip Select 1 */
225 ldr r1, VAL_TC_EMIFS_CS2_CONFIG
226 ldr r0, REG_TC_EMIFS_CS2_CONFIG
227 str r1, [r0] /* Chip Select 2 */
228 ldr r1, VAL_TC_EMIFS_CS3_CONFIG
229 ldr r0, REG_TC_EMIFS_CS3_CONFIG
230 str r1, [r0] /* Chip Select 3 */
232 /* back to arch calling code */
235 /* the literal pools origin */
238 /* OMAP configuration registers */
239 REG_FUNC_MUX_CTRL_0: /* 32 bits */
241 REG_FUNC_MUX_CTRL_1: /* 32 bits */
243 REG_FUNC_MUX_CTRL_2: /* 32 bits */
245 REG_COMP_MODE_CTRL_0: /* 32 bits */
247 REG_FUNC_MUX_CTRL_3: /* 32 bits */
249 REG_FUNC_MUX_CTRL_4: /* 32 bits */
251 REG_FUNC_MUX_CTRL_5: /* 32 bits */
253 REG_FUNC_MUX_CTRL_6: /* 32 bits */
255 REG_FUNC_MUX_CTRL_7: /* 32 bits */
257 REG_FUNC_MUX_CTRL_8: /* 32 bits */
259 REG_FUNC_MUX_CTRL_9: /* 32 bits */
261 REG_FUNC_MUX_CTRL_A: /* 32 bits */
263 REG_FUNC_MUX_CTRL_B: /* 32 bits */
265 REG_FUNC_MUX_CTRL_C: /* 32 bits */
267 REG_FUNC_MUX_CTRL_D: /* 32 bits */
269 REG_PULL_DWN_CTRL_0: /* 32 bits */
271 REG_PULL_DWN_CTRL_1: /* 32 bits */
273 REG_PULL_DWN_CTRL_2: /* 32 bits */
275 REG_PULL_DWN_CTRL_3: /* 32 bits */
277 REG_VOLTAGE_CTRL_0: /* 32 bits */
279 REG_TEST_DBG_CTRL_0: /* 32 bits */
281 REG_MOD_CONF_CTRL_0: /* 32 bits */
283 REG_TC_IMIF_PRIO: /* 32 bits */
285 REG_TC_EMIFS_PRIO: /* 32 bits */
287 REG_TC_EMIFF_PRIO: /* 32 bits */
289 REG_TC_EMIFS_CONFIG: /* 32 bits */
291 REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
293 REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
295 REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
297 REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
299 REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */
301 REG_TC_EMIFF_MRS: /* 32 bits */
303 /* MPU clock/reset/power mode control registers */
304 REG_ARM_CKCTL: /* 16 bits */
306 REG_ARM_IDLECT2: /* 16 bits */
308 REG_ARM_RSTCT2: /* 16 bits */
310 REG_ARM_SYSST: /* 16 bits */
312 /* DPLL control registers */
313 REG_DPLL1_CTL: /* 16 bits */
315 /* identification code register */
316 REG_IDCODE: /* 32 bits */
320 _GPIO_PIN_CONTROL_REG:
321 .word GPIO_PIN_CONTROL_REG
322 _GPIO_DIR_CONTROL_REG:
323 .word GPIO_DIR_CONTROL_REG
324 _GPIO_DATA_OUTPUT_REG:
325 .word GPIO_DATA_OUTPUT_REG
327 VAL_COMP_MODE_CTRL_0:
338 .word 0x00001240 /*[Knoller] Value of Symbian Image Wing B2*/
346 .word 0x09008001 /*[Knoller] Value of Symbian Image Wing B2*/
360 /* The OMAP5910 TRM says this register must be 0, but HelenConfRegs
361 * says to write a 7. Don't know what the right thing is to do, so
362 * I'm leaving it at 7 since that's what was already here.
366 .word 0x0da20000 /*[Knoller] Value of Symbian Image Wing B2*/
372 .word 0x3A33 /*[Hertle] Value of Symbian Image*/
374 VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
377 VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
380 VAL_TC_EMIFS_CS0_CONFIG:
381 .word 0x00213090 /*[Knoller] Value of Symbian Image Wing B2*/
383 VAL_TC_EMIFS_CS1_CONFIG:
384 .word 0x00215070 /*[Knoller] Value of Symbian Image Wing B2*/
386 VAL_TC_EMIFS_CS2_CONFIG:
387 .word 0x00001139 /*[Knoller] Value of Symbian Image Wing B2*/
389 VAL_TC_EMIFS_CS3_CONFIG:
390 .word 0x00001139 /*[Knoller] Value of Symbian Image Wing B2*/
392 VAL_TC_EMIFF_SDRAM_CONFIG:
393 .word 0x0105f0b4 /*[Knoller] Value of Symbian Image Wing B2*/
397 .word 0x00000027 /*[Knoller] Value of Symbian Image Wing B2*/