3 * Matthias Weisser <weisserm@arcor.de>
5 * (C) Copyright 2009 DENX Software Engineering
6 * Author: John Rigby <jrigby@gmail.com>
8 * Based on U-Boot and RedBoot sources for several different i.mx
11 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/macro.h>
15 #include <asm/arch/macro.h>
16 #include <asm/arch/imx-regs.h>
17 #include <generated/asm-offsets.h>
24 /* disable clock output */
25 write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
26 write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
29 * enable all implemented clocks in all three
30 * clock control registers
32 write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
33 write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
34 write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
36 /* Devide NAND clock by 32 */
37 write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
41 * sdram controller init
44 ldr r0, =IMX_ESDRAMC_BASE
45 ldr r2, =IMX_SDRAM_BANK0_BASE
48 * reset SDRAM controller
49 * then wait for initialization to complete
51 ldr r1, =(1 << 1) | (1 << 2)
52 str r1, [r0, #ESDRAMC_ESDMISC]
53 1: ldr r3, [r0, #ESDRAMC_ESDMISC]
57 str r1, [r0, #ESDRAMC_ESDMISC]
60 str r1, [r0, #ESDRAMC_ESDCFG0]
62 /* control | precharge */
64 str r1, [r0, #ESDRAMC_ESDCTL0]
65 /* dram command encoded in address */
70 str r1, [r0, #ESDRAMC_ESDCTL0]
71 /* read dram twice to auto refresh */
75 /* control | load mode */
77 str r1, [r0, #ESDRAMC_ESDCTL0]
79 /* mode register of lpddram */
82 /* extended mode register of lpddrram */
86 /* control | normal */
88 str r1, [r0, #ESDRAMC_ESDCTL0]