2 * (c) 2011 Graf-Syteco, Matthias Weisser
6 * (C) Copyright 2009 DENX Software Engineering
7 * Author: John Rigby <jrigby@gmail.com>
9 * Based on imx27lite.c:
10 * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
11 * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
13 * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/arch/imx-regs.h>
35 #include <asm/arch/imx25-pinmux.h>
36 #include <asm/arch/sys_proto.h>
38 DECLARE_GLOBAL_DATA_PTR;
42 struct iomuxc_mux_ctl *muxctl;
43 struct iomuxc_pad_ctl *padctl;
44 struct iomuxc_pad_input_select *inputselect;
45 u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
46 u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
47 u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
48 u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
49 u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
50 u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
54 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
55 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
56 inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
58 /* Setup of core volatage selection pin to run at 1.4V */
59 writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
60 gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
62 /* Setup of input daisy chains for SD card pins*/
63 writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
64 writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
65 writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
66 writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
67 writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
68 writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
70 /* Setup of digital output for USB power and OC */
71 writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
72 gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
74 writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
75 gpio_direction_input(IMX_GPIO_NR(1, 18));
77 /* Setup of digital output control pins */
78 writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
79 writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
80 writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
81 writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
83 writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
84 writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
86 /* Switch both output drivers off */
87 gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
88 gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
90 /* Setup of key input pin GPIO2[29]*/
91 writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
92 writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
93 gpio_direction_input(IMX_GPIO_NR(2, 29));
95 /* Setup of status LED outputs */
96 writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */
97 writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */
99 /* Switch both LEDs off */
100 gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
101 gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
103 /* Setup of CAN1 and CAN2 signals */
104 writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */
105 writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */
106 writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */
107 writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */
109 /* Setup of input daisy chains for CAN signals*/
110 writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
111 writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
113 /* Setup of I2C3 signals */
114 writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */
115 writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */
117 /* Setup of input daisy chains for I2C3 signals*/
118 writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */
119 writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */
121 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
126 int board_late_init(void)
130 #ifdef CONFIG_FEC_MXC
131 struct iomuxc_mux_ctl *muxctl;
132 u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
133 u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
136 * fec pin init is generic
138 mx25_fec_init_pins();
141 * Set up LAN-RESET and FEC_RX_ERR
143 * LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20
144 * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
146 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
148 writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
149 writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
151 /* assert PHY reset (low) */
152 gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
156 /* deassert PHY reset */
157 gpio_set_value(IMX_GPIO_NR(3, 16), 1);
162 e = getenv("gs_base_board");
164 if (strcmp(e, "G283") == 0) {
165 int key = gpio_get_value(IMX_GPIO_NR(2, 29));
168 /* Switch on both LEDs to inidcate boot mode */
169 gpio_set_value(IMX_GPIO_NR(1, 29), 0);
170 gpio_set_value(IMX_GPIO_NR(4, 21), 0);
172 setenv("preboot", "run gs_slow_boot");
174 setenv("preboot", "run gs_fast_boot");
183 /* dram_init must store complete ramsize in gd->ram_size */
184 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,