2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * Achim Ehrlich <aehrlich@taskit.de>
7 * taskit GmbH <www.taskit.de>
10 * Markus Hubig <mhubig@imko.de>
11 * IMKO GmbH <www.imko.de>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/arch/at91sam9260_matrix.h>
35 #include <asm/arch/at91sam9_smc.h>
36 #include <asm/arch/at91_common.h>
37 #include <asm/arch/at91_pmc.h>
38 #include <asm/arch/at91_rstc.h>
39 #include <asm/arch/gpio.h>
47 DECLARE_GLOBAL_DATA_PTR;
49 static void stamp9G20_nand_hw_init(void)
51 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
52 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
55 /* Assign CS3 to NAND/SmartMedia Interface */
56 csa = readl(&matrix->ebicsa);
57 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
58 writel(csa, &matrix->ebicsa);
60 /* Configure SMC CS3 for NAND/SmartMedia */
61 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
62 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
64 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
65 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
67 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
69 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
70 AT91_SMC_MODE_EXNW_DISABLE |
72 AT91_SMC_MODE_TDF_CYCLE(2),
75 /* Configure RDY/BSY */
76 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
78 /* Enable NandFlash */
79 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
83 static void stamp9G20_macb_hw_init(void)
85 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
86 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
89 /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
90 at91_set_gpio_output(AT91_PIN_PA26, 0);
94 * RXDV (PA17) => PHY normal mode (not Test mode)
95 * ERX0 (PA14) => PHY ADDR0
96 * ERX1 (PA15) => PHY ADDR1
97 * ERX2 (PA25) => PHY ADDR2
98 * ERX3 (PA26) => PHY ADDR3
99 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
101 * PHY has internal pull-down
103 writel(pin_to_mask(AT91_PIN_PA14) |
104 pin_to_mask(AT91_PIN_PA15) |
105 pin_to_mask(AT91_PIN_PA17) |
106 pin_to_mask(AT91_PIN_PA18) |
107 pin_to_mask(AT91_PIN_PA28),
110 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
112 /* Need to reset PHY -> 500ms reset */
113 writel(AT91_RSTC_KEY | (AT91_RSTC_MR_ERSTL(13) &
114 ~AT91_RSTC_MR_URSTEN), &rstc->mr);
115 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
117 /* Wait for end of hardware reset */
118 unsigned long start = get_timer(0);
119 unsigned long timeout = 1000; /* 1000ms */
121 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
123 /* avoid shutdown by watchdog */
127 /* timeout for not getting stuck in an endless loop */
128 if (get_timer(start) >= timeout) {
129 puts("*** ERROR: Timeout waiting for PHY reset!\n");
134 /* Restore NRST value */
135 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
138 /* Re-enable pull-up */
139 writel(pin_to_mask(AT91_PIN_PA14) |
140 pin_to_mask(AT91_PIN_PA15) |
141 pin_to_mask(AT91_PIN_PA17) |
142 pin_to_mask(AT91_PIN_PA18) |
143 pin_to_mask(AT91_PIN_PA28),
146 /* Initialize EMAC=MACB hardware */
149 #endif /* CONFIG_MACB */
151 int board_early_init_f(void)
153 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
155 /* Enable clocks for all PIOs */
156 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
157 (1 << ATMEL_ID_PIOC), &pmc->pcer);
164 /* Adress of boot parameters */
165 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
167 /* Enable the serial interface */
168 at91_set_gpio_output(AT91_PIN_PC9, 1);
169 at91_seriald_hw_init();
171 stamp9G20_nand_hw_init();
173 stamp9G20_macb_hw_init();
180 gd->ram_size = get_ram_size(
181 (void *)CONFIG_SYS_SDRAM_BASE,
182 CONFIG_SYS_SDRAM_SIZE);
187 int board_eth_init(bd_t *bis)
189 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
191 #endif /* CONFIG_MACB */