git.sur5r.net Git - u-boot/blob - board/tcl/sl50/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TCL SL50 board
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <spl.h>
  13 #include <asm/arch/cpu.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/omap.h>
  16 #include <asm/arch/ddr_defs.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/mmc_host_def.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/arch/mem.h>
  22 #include <asm/io.h>
  23 #include <asm/emif.h>
  24 #include <asm/gpio.h>
  25 #include <i2c.h>
  26 #include <miiphy.h>
  27 #include <cpsw.h>
  28 #include <power/tps65217.h>
  29 #include <power/tps65910.h>
  30 #include <environment.h>
  31 #include <watchdog.h>
  32 #include <environment.h>
  33 #include "board.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  38
  39 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  40
  41 static const struct ddr_data ddr3_sl50_data = {
  42         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  43         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  44         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  45         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  46 };
  47
  48 static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
  49         .cmd0csratio = MT41K256M16HA125E_RATIO,
  50         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  51
  52         .cmd1csratio = MT41K256M16HA125E_RATIO,
  53         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  54
  55         .cmd2csratio = MT41K256M16HA125E_RATIO,
  56         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  57 };
  58
  59 static struct emif_regs ddr3_sl50_emif_reg_data = {
  60         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  61         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  62         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  63         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  64         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  65         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  66         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  67 };
  68
  69 #ifdef CONFIG_SPL_OS_BOOT
  70 int spl_start_uboot(void)
  71 {
  72         /* break into full u-boot on 'c' */
  73         if (serial_tstc() && serial_getc() == 'c')
  74                 return 1;
  75
  76 #ifdef CONFIG_SPL_ENV_SUPPORT
  77         env_init();
  78         env_load();
  79         if (env_get_yesno("boot_os") != 1)
  80                 return 1;
  81 #endif
  82
  83         return 0;
  84 }
  85 #endif
  86
  87 #define OSC     (V_OSCK/1000000)
  88 const struct dpll_params dpll_ddr_sl50 = {
  89                 400, OSC-1, 1, -1, -1, -1, -1};
  90
  91 void am33xx_spl_board_init(void)
  92 {
  93         int mpu_vdd;
  94
  95         /* Get the frequency */
  96         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  97
  98         /* BeagleBone PMIC Code */
  99         int usb_cur_lim;
 100
 101         if (i2c_probe(TPS65217_CHIP_PM))
 102                 return;
 103
 104         /*
 105          * Increase USB current limit to 1300mA or 1800mA and set
 106          * the MPU voltage controller as needed.
 107          */
 108         if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 109                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 110                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 111         } else {
 112                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 113                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 114         }
 115
 116         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 117                                TPS65217_POWER_PATH,
 118                                usb_cur_lim,
 119                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 120                 puts("tps65217_reg_write failure\n");
 121
 122         /* Set DCDC3 (CORE) voltage to 1.125V */
 123         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 124                                     TPS65217_DCDC_VOLT_SEL_1125MV)) {
 125                 puts("tps65217_voltage_update failure\n");
 126                 return;
 127         }
 128
 129         /* Set CORE Frequencies to OPP100 */
 130         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 131
 132         /* Set DCDC2 (MPU) voltage */
 133         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 134                 puts("tps65217_voltage_update failure\n");
 135                 return;
 136         }
 137
 138         /*
 139          * Set LDO3 to 1.8V and LDO4 to 3.3V
 140          */
 141         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 142                                TPS65217_DEFLS1,
 143                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 144                                TPS65217_LDO_MASK))
 145                 puts("tps65217_reg_write failure\n");
 146
 147         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 148                                TPS65217_DEFLS2,
 149                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 150                                TPS65217_LDO_MASK))
 151                 puts("tps65217_reg_write failure\n");
 152
 153         /* Set MPU Frequency to what we detected now that voltages are set */
 154         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 155 }
 156
 157 const struct dpll_params *get_dpll_ddr_params(void)
 158 {
 159         enable_i2c0_pin_mux();
 160         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 161
 162         return &dpll_ddr_sl50;
 163 }
 164
 165 void set_uart_mux_conf(void)
 166 {
 167 #if CONFIG_CONS_INDEX == 1
 168         enable_uart0_pin_mux();
 169 #elif CONFIG_CONS_INDEX == 2
 170         enable_uart1_pin_mux();
 171 #elif CONFIG_CONS_INDEX == 3
 172         enable_uart2_pin_mux();
 173 #elif CONFIG_CONS_INDEX == 4
 174         enable_uart3_pin_mux();
 175 #elif CONFIG_CONS_INDEX == 5
 176         enable_uart4_pin_mux();
 177 #elif CONFIG_CONS_INDEX == 6
 178         enable_uart5_pin_mux();
 179 #endif
 180 }
 181
 182 void set_mux_conf_regs(void)
 183 {
 184         enable_board_pin_mux();
 185 }
 186
 187 const struct ctrl_ioregs ioregs_evmsk = {
 188         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 189         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 190         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 191         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 192         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 193 };
 194
 195 const struct ctrl_ioregs ioregs_bonelt = {
 196         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 197         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 198         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 199         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 200         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 201 };
 202
 203 const struct ctrl_ioregs ioregs_evm15 = {
 204         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 205         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 206         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 207         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 208         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 209 };
 210
 211 const struct ctrl_ioregs ioregs = {
 212         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 213         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 214         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 215         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 216         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 217 };
 218
 219 void sdram_init(void)
 220 {
 221         config_ddr(400, &ioregs_bonelt,
 222                    &ddr3_sl50_data,
 223                    &ddr3_sl50_cmd_ctrl_data,
 224                    &ddr3_sl50_emif_reg_data, 0);
 225 }
 226 #endif
 227
 228 /*
 229  * Basic board specific setup.  Pinmux has been handled already.
 230  */
 231 int board_init(void)
 232 {
 233 #if defined(CONFIG_HW_WATCHDOG)
 234         hw_watchdog_init();
 235 #endif
 236
 237         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 238         return 0;
 239 }
 240
 241 #ifdef CONFIG_BOARD_LATE_INIT
 242 int board_late_init(void)
 243 {
 244         return 0;
 245 }
 246 #endif
 247
 248 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 249         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 250 static void cpsw_control(int enabled)
 251 {
 252         /* VTP can be added here */
 253
 254         return;
 255 }
 256
 257 static struct cpsw_slave_data cpsw_slaves[] = {
 258         {
 259                 .slave_reg_ofs  = 0x208,
 260                 .sliver_reg_ofs = 0xd80,
 261                 .phy_addr       = 0,
 262         },
 263         {
 264                 .slave_reg_ofs  = 0x308,
 265                 .sliver_reg_ofs = 0xdc0,
 266                 .phy_addr       = 1,
 267         },
 268 };
 269
 270 static struct cpsw_platform_data cpsw_data = {
 271         .mdio_base              = CPSW_MDIO_BASE,
 272         .cpsw_base              = CPSW_BASE,
 273         .mdio_div               = 0xff,
 274         .channels               = 8,
 275         .cpdma_reg_ofs          = 0x800,
 276         .slaves                 = 1,
 277         .slave_data             = cpsw_slaves,
 278         .ale_reg_ofs            = 0xd00,
 279         .ale_entries            = 1024,
 280         .host_port_reg_ofs      = 0x108,
 281         .hw_stats_reg_ofs       = 0x900,
 282         .bd_ram_ofs             = 0x2000,
 283         .mac_control            = (1 << 5),
 284         .control                = cpsw_control,
 285         .host_port_num          = 0,
 286         .version                = CPSW_CTRL_VERSION_2,
 287 };
 288 #endif
 289
 290 /*
 291  * This function will:
 292  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 293  * in the environment
 294  * Perform fixups to the PHY present on certain boards.  We only need this
 295  * function in:
 296  * - SPL with either CPSW or USB ethernet support
 297  * - Full U-Boot, with either CPSW or USB ethernet
 298  * Build in only these cases to avoid warnings about unused variables
 299  * when we build an SPL that has neither option but full U-Boot will.
 300  */
 301 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
 302                 && defined(CONFIG_SPL_BUILD)) || \
 303         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 304           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 305          !defined(CONFIG_SPL_BUILD))
 306 int board_eth_init(bd_t *bis)
 307 {
 308         int rv, n = 0;
 309         uint8_t mac_addr[6];
 310         uint32_t mac_hi, mac_lo;
 311
 312         /* try reading mac address from efuse */
 313         mac_lo = readl(&cdev->macid0l);
 314         mac_hi = readl(&cdev->macid0h);
 315         mac_addr[0] = mac_hi & 0xFF;
 316         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 317         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 318         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 319         mac_addr[4] = mac_lo & 0xFF;
 320         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 321
 322 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 323         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 324         if (!env_get("ethaddr")) {
 325                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 326
 327                 if (is_valid_ethaddr(mac_addr))
 328                         eth_env_set_enetaddr("ethaddr", mac_addr);
 329         }
 330
 331 #ifdef CONFIG_DRIVER_TI_CPSW
 332
 333         mac_lo = readl(&cdev->macid1l);
 334         mac_hi = readl(&cdev->macid1h);
 335         mac_addr[0] = mac_hi & 0xFF;
 336         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 337         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 338         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 339         mac_addr[4] = mac_lo & 0xFF;
 340         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 341
 342         if (!env_get("eth1addr")) {
 343                 if (is_valid_ethaddr(mac_addr))
 344                         eth_env_set_enetaddr("eth1addr", mac_addr);
 345         }
 346
 347
 348         writel(MII_MODE_ENABLE, &cdev->miisel);
 349         cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 350                                 PHY_INTERFACE_MODE_MII;
 351
 352         rv = cpsw_register(&cpsw_data);
 353         if (rv < 0)
 354                 printf("Error %d registering CPSW switch\n", rv);
 355         else
 356                 n += rv;
 357 #endif
 358
 359         /*
 360          *
 361          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 362          * operating points.  So we must set the TX clock delay feature
 363          * in the AR8051 PHY.  Since we only support a single ethernet
 364          * device in U-Boot, we only do this for the first instance.
 365          */
 366 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 367 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 368 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 369 #define AR8051_RGMII_TX_CLK_DLY         0x100
 370
 371 #endif
 372 #if defined(CONFIG_USB_ETHER) && \
 373         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
 374         if (is_valid_ether_addr(mac_addr))
 375                 eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
 376
 377         rv = usb_eth_initialize(bis);
 378         if (rv < 0)
 379                 printf("Error %d registering USB_ETHER\n", rv);
 380         else
 381                 n += rv;
 382 #endif
 383         return n;
 384 }
 385 #endif