2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/soc.h>
15 #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
16 #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
18 DECLARE_GLOBAL_DATA_PTR;
20 #define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
21 #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
22 #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
24 #define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
25 #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
26 #define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
28 /* DDR3 static configuration */
29 static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
30 {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
31 {0x00001404, 0x30000800}, /* Dunit Control Low Register */
32 {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
33 {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
34 {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
35 {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
36 {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
37 {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
38 {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
40 {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
41 {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
42 {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
43 {0x000014A8, 0x00000101}, /* AXI Control Register */
46 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
49 {0x000200e8, 0x3fff0e01},
50 {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
52 {0x0001504, 0x7fffffe1}, /* CS0 Size */
53 {0x000150C, 0x00000000}, /* CS1 Size */
54 {0x0001514, 0x00000000}, /* CS2 Size */
55 {0x000151C, 0x00000000}, /* CS3 Size */
57 {0x00020220, 0x00000007}, /* Reserved */
59 {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
60 {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
62 {0x000015D0, 0x00000650}, /* MR0 */
63 {0x000015D4, 0x00000044}, /* MR1 */
64 {0x000015D8, 0x00000010}, /* MR2 */
65 {0x000015DC, 0x00000000}, /* MR3 */
66 {0x000015E0, 0x00000001},
67 {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
68 {0x000015EC, 0xf800a225}, /* DDR PHY */
70 /* Recommended Settings from Marvell for 4 x 16 bit devices: */
71 {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
72 {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
77 static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
78 {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
81 extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
84 * Lane0 - PCIE0.0 X1 (to WIFI Module)
87 * Lane7 - SGMII0 (to Ethernet Phy)
88 * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
89 * all other lanes are disabled
91 MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
92 { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
93 { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
95 0x0060, serdes_change_m_phy
99 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
101 /* Only one mode supported for this board */
102 return &board_ddr_modes[0];
105 MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
107 return &theadorable_serdes_cfg[0];
110 int board_early_init_f(void)
113 writel(0x00000000, MVEBU_MPP_BASE + 0x00);
114 writel(0x03300000, MVEBU_MPP_BASE + 0x04);
115 writel(0x00000033, MVEBU_MPP_BASE + 0x08);
116 writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
117 writel(0x11110000, MVEBU_MPP_BASE + 0x10);
118 writel(0x00221100, MVEBU_MPP_BASE + 0x14);
119 writel(0x00000000, MVEBU_MPP_BASE + 0x18);
120 writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
121 writel(0x00000000, MVEBU_MPP_BASE + 0x20);
124 writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
125 writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
126 writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
127 writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
128 writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
129 writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
136 /* adress of boot parameters */
137 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
144 puts("Board: theadorable\n");
150 int board_eth_init(bd_t *bis)
152 cpu_eth_init(bis); /* Built in controller(s) come first */
153 return pci_eth_init(bis);
157 int board_video_init(void)
159 struct mvebu_lcd_info lcd_info;
161 /* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */
162 lcd_info.fb_base = gd->ram_size;
163 lcd_info.x_res = 240;
166 lcd_info.y_res = 320;
170 return mvebu_lcd_register_init(&lcd_info);