1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 #include <linux/crc8.h>
14 #include <linux/mbus.h>
18 #include "theadorable.h"
20 #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
21 #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
26 #define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
27 (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
29 #define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
30 #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
31 #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
33 #define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
34 #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
35 #define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
37 #define GPIO_USB0_PWR_ON 18
38 #define GPIO_USB1_PWR_ON 19
40 #define PEX_SWITCH_NOT_FOUNT_LIMIT 3
43 #define STM_I2C_ADDR 0x27
44 #define REBOOT_DELAY 1000 /* reboot-delay in ms */
46 /* DDR3 static configuration */
47 static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
48 {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
49 {0x00001404, 0x30000800}, /* Dunit Control Low Register */
50 {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
51 {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
52 {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
53 {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
54 {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
55 {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
56 {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
58 {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
59 {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
60 {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
61 {0x000014A8, 0x00000101}, /* AXI Control Register */
64 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
67 {0x000200e8, 0x3fff0e01},
68 {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
70 {0x0001504, 0x7fffffe1}, /* CS0 Size */
71 {0x000150C, 0x00000000}, /* CS1 Size */
72 {0x0001514, 0x00000000}, /* CS2 Size */
73 {0x000151C, 0x00000000}, /* CS3 Size */
75 {0x00020220, 0x00000007}, /* Reserved */
77 {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
78 {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
80 {0x000015D0, 0x00000650}, /* MR0 */
81 {0x000015D4, 0x00000044}, /* MR1 */
82 {0x000015D8, 0x00000010}, /* MR2 */
83 {0x000015DC, 0x00000000}, /* MR3 */
84 {0x000015E0, 0x00000001},
85 {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
86 {0x000015EC, 0xf800a225}, /* DDR PHY */
88 /* Recommended Settings from Marvell for 4 x 16 bit devices: */
89 {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
90 {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
95 static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
96 {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
99 extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
102 * Lane0 - PCIE0.0 X1 (to WIFI Module)
105 * Lane7 - SGMII0 (to Ethernet Phy)
106 * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
107 * all other lanes are disabled
109 MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
110 { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
111 { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
113 0x0060, serdes_change_m_phy
118 * Define a board-specific detection pulse-width array for the SerDes PCIe
119 * interfaces. If not defined in the board code, the default of currently 2
120 * is used. Values from 0...3 are possible (2 bits).
122 u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
124 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
126 /* Only one mode supported for this board */
127 return &board_ddr_modes[0];
130 MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
132 return &theadorable_serdes_cfg[0];
135 u8 board_sat_r_get(u8 dev_num, u8 reg)
137 /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
141 int board_early_init_f(void)
144 writel(0x00000000, MVEBU_MPP_BASE + 0x00);
145 writel(0x03300000, MVEBU_MPP_BASE + 0x04);
146 writel(0x00000033, MVEBU_MPP_BASE + 0x08);
147 writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
148 writel(0x11110000, MVEBU_MPP_BASE + 0x10);
149 writel(0x00221100, MVEBU_MPP_BASE + 0x14);
150 writel(0x00000000, MVEBU_MPP_BASE + 0x18);
151 writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
152 writel(0x00000000, MVEBU_MPP_BASE + 0x20);
155 writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
156 writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
157 writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
158 writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
159 writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
160 writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
169 /* adress of boot parameters */
170 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
173 * Map SPI devices via MBUS so that they can be accessed via
174 * the SPI direct access mode
176 mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
177 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
178 mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
179 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
182 * Set RX Channel Control 0 Register:
183 * Tests have shown, that setting the LPF_COEF from 0 (1/8)
184 * to 3 (1/1) results in a more stable USB connection.
186 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
187 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
188 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
190 /* Toggle USB power */
191 ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
194 gpio_direction_output(GPIO_USB0_PWR_ON, 0);
195 ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
198 gpio_direction_output(GPIO_USB1_PWR_ON, 0);
200 gpio_set_value(GPIO_USB0_PWR_ON, 1);
201 gpio_set_value(GPIO_USB1_PWR_ON, 1);
214 int board_eth_init(bd_t *bis)
216 cpu_eth_init(bis); /* Built in controller(s) come first */
217 return pci_eth_init(bis);
221 int board_video_init(void)
223 struct mvebu_lcd_info lcd_info;
225 /* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */
226 lcd_info.fb_base = gd->ram_size;
227 lcd_info.x_res = 240;
230 lcd_info.y_res = 320;
234 return mvebu_lcd_register_init(&lcd_info);
237 #ifdef CONFIG_BOARD_LATE_INIT
238 int board_late_init(void)
244 * Check if the PEX switch is detected (somtimes its not available
245 * on the PCIe bus). In this case, try to recover by issuing a
246 * soft-reset or even a power-cycle, depending on the bootcounter
249 bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
254 /* PEX switch not found! */
255 bootcount = bootcount_load();
256 printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
258 if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
259 printf("Issuing power-switch via uC!\n");
261 printf("Issuing power-switch via uC!\n");
262 i2c_set_bus_num(STM_I2C_BUS);
263 i2c_buf[0] = STM_I2C_ADDR << 1;
264 i2c_buf[1] = 0xc5; /* cmd */
265 i2c_buf[2] = 0x01; /* enable */
266 /* Delay before reboot */
267 i2c_buf[3] = REBOOT_DELAY & 0x00ff;
268 i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
269 /* Delay before shutdown */
272 i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
274 ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
276 printf("I2C write error (ret=%d)\n", ret);
277 printf("Issuing soft-reset...\n");
278 /* default handling: SOFT reset */
279 do_reset(NULL, 0, 0, NULL);
282 /* Wait for power-cycle to occur... */
283 printf("Waiting for power-cycle via uC...\n");
287 printf("Issuing soft-reset...\n");
288 /* default handling: SOFT reset */
289 do_reset(NULL, 0, 0, NULL);
297 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
298 int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
304 return cmd_usage(cmdtp);
306 ven_id = simple_strtoul(argv[1], NULL, 16);
307 dev_id = simple_strtoul(argv[2], NULL, 16);
309 printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
313 * Check if the PCIe device is detected (somtimes its not available
316 bdf = pci_find_device(ven_id, dev_id, 0);
318 /* PCIe device not found! */
319 printf("Failed to find PCIe device\n");
321 /* PCIe device found! */
322 printf("PCIe device found, resetting board...\n");
324 /* default handling: SOFT reset */
325 do_reset(NULL, 0, 0, NULL);
332 pcie, 3, 0, do_pcie_test,
333 "Test for presence of a PCIe device",
334 "<VendorID> <DeviceID>"