4 * Board functions for TI AM335X based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
29 #include <power/tps65217.h>
30 #include <power/tps65910.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 /* GPIO that controls power to DDR on EVM-SK */
36 #define GPIO_DDR_VTT_EN 7
38 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
41 * Read header information from EEPROM into global structure.
43 static int read_eeprom(struct am335x_baseboard_id *header)
45 /* Check if baseboard eeprom is available */
46 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
47 puts("Could not probe the EEPROM; something fundamentally "
48 "wrong on the I2C bus.\n");
52 /* read the eeprom using i2c */
53 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
54 sizeof(struct am335x_baseboard_id))) {
55 puts("Could not read the EEPROM; something fundamentally"
56 " wrong on the I2C bus.\n");
60 if (header->magic != 0xEE3355AA) {
62 * read the eeprom using i2c again,
63 * but use only a 1 byte address
65 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
66 sizeof(struct am335x_baseboard_id))) {
67 puts("Could not read the EEPROM; something "
68 "fundamentally wrong on the I2C bus.\n");
72 if (header->magic != 0xEE3355AA) {
73 printf("Incorrect magic number (0x%x) in EEPROM\n",
82 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
83 static const struct ddr_data ddr2_data = {
84 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
85 (MT47H128M16RT25E_RD_DQS<<20) |
86 (MT47H128M16RT25E_RD_DQS<<10) |
87 (MT47H128M16RT25E_RD_DQS<<0)),
88 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
89 (MT47H128M16RT25E_WR_DQS<<20) |
90 (MT47H128M16RT25E_WR_DQS<<10) |
91 (MT47H128M16RT25E_WR_DQS<<0)),
92 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
93 (MT47H128M16RT25E_PHY_WRLVL<<20) |
94 (MT47H128M16RT25E_PHY_WRLVL<<10) |
95 (MT47H128M16RT25E_PHY_WRLVL<<0)),
96 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
97 (MT47H128M16RT25E_PHY_GATELVL<<20) |
98 (MT47H128M16RT25E_PHY_GATELVL<<10) |
99 (MT47H128M16RT25E_PHY_GATELVL<<0)),
100 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
101 (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
102 (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
103 (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
104 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
105 (MT47H128M16RT25E_PHY_WR_DATA<<20) |
106 (MT47H128M16RT25E_PHY_WR_DATA<<10) |
107 (MT47H128M16RT25E_PHY_WR_DATA<<0)),
108 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
109 .datadldiff0 = PHY_DLL_LOCK_DIFF,
112 static const struct cmd_control ddr2_cmd_ctrl_data = {
113 .cmd0csratio = MT47H128M16RT25E_RATIO,
114 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
115 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
117 .cmd1csratio = MT47H128M16RT25E_RATIO,
118 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
119 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
121 .cmd2csratio = MT47H128M16RT25E_RATIO,
122 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
123 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
126 static const struct emif_regs ddr2_emif_reg_data = {
127 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
128 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
129 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
130 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
131 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
132 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
135 static const struct ddr_data ddr3_data = {
136 .datardsratio0 = MT41J128MJT125_RD_DQS,
137 .datawdsratio0 = MT41J128MJT125_WR_DQS,
138 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
139 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
140 .datadldiff0 = PHY_DLL_LOCK_DIFF,
143 static const struct ddr_data ddr3_beagleblack_data = {
144 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
145 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
146 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
147 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
148 .datadldiff0 = PHY_DLL_LOCK_DIFF,
151 static const struct ddr_data ddr3_evm_data = {
152 .datardsratio0 = MT41J512M8RH125_RD_DQS,
153 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
154 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
155 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
156 .datadldiff0 = PHY_DLL_LOCK_DIFF,
159 static const struct cmd_control ddr3_cmd_ctrl_data = {
160 .cmd0csratio = MT41J128MJT125_RATIO,
161 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
162 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
164 .cmd1csratio = MT41J128MJT125_RATIO,
165 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
166 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
168 .cmd2csratio = MT41J128MJT125_RATIO,
169 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
170 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
173 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
174 .cmd0csratio = MT41K256M16HA125E_RATIO,
175 .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
176 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
178 .cmd1csratio = MT41K256M16HA125E_RATIO,
179 .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
180 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
182 .cmd2csratio = MT41K256M16HA125E_RATIO,
183 .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
184 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
187 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
188 .cmd0csratio = MT41J512M8RH125_RATIO,
189 .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
190 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
192 .cmd1csratio = MT41J512M8RH125_RATIO,
193 .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
194 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
196 .cmd2csratio = MT41J512M8RH125_RATIO,
197 .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
198 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
201 static struct emif_regs ddr3_emif_reg_data = {
202 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
203 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
204 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
205 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
206 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
207 .zq_config = MT41J128MJT125_ZQ_CFG,
208 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
212 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
213 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
214 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
215 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
216 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
217 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
218 .zq_config = MT41K256M16HA125E_ZQ_CFG,
219 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
222 static struct emif_regs ddr3_evm_emif_reg_data = {
223 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
224 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
225 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
226 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
227 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
228 .zq_config = MT41J512M8RH125_ZQ_CFG,
229 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
233 #ifdef CONFIG_SPL_OS_BOOT
234 int spl_start_uboot(void)
236 /* break into full u-boot on 'c' */
237 return (serial_tstc() && serial_getc() == 'c');
241 #define OSC (V_OSCK/1000000)
242 const struct dpll_params dpll_ddr = {
243 266, OSC-1, 1, -1, -1, -1, -1};
244 const struct dpll_params dpll_ddr_evm_sk = {
245 303, OSC-1, 1, -1, -1, -1, -1};
246 const struct dpll_params dpll_ddr_bone_black = {
247 400, OSC-1, 1, -1, -1, -1, -1};
249 void am33xx_spl_board_init(void)
251 struct am335x_baseboard_id header;
254 if (read_eeprom(&header) < 0)
255 puts("Could not get board ID.\n");
257 /* Get the frequency */
258 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
260 if (board_is_bone(&header) || board_is_bone_lt(&header)) {
261 /* BeagleBone PMIC Code */
265 * Only perform PMIC configurations if board rev > A1
266 * on Beaglebone White
268 if (board_is_bone(&header) && !strncmp(header.version,
272 if (i2c_probe(TPS65217_CHIP_PM))
276 * On Beaglebone White we need to ensure we have AC power
277 * before increasing the frequency.
279 if (board_is_bone(&header)) {
280 uchar pmic_status_reg;
281 if (tps65217_reg_read(TPS65217_STATUS,
284 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
285 puts("No AC power, disabling frequency switch\n");
291 * Override what we have detected since we know if we have
292 * a Beaglebone Black it supports 1GHz.
294 if (board_is_bone_lt(&header))
295 dpll_mpu_opp100.m = MPUPLL_M_1000;
298 * Increase USB current limit to 1300mA or 1800mA and set
299 * the MPU voltage controller as needed.
301 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
302 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
303 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
305 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
306 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
309 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
312 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
313 puts("tps65217_reg_write failure\n");
315 /* Set DCDC3 (CORE) voltage to 1.125V */
316 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
317 TPS65217_DCDC_VOLT_SEL_1125MV)) {
318 puts("tps65217_voltage_update failure\n");
322 /* Set CORE Frequencies to OPP100 */
323 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
325 /* Set DCDC2 (MPU) voltage */
326 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
327 puts("tps65217_voltage_update failure\n");
332 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
333 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
335 if (board_is_bone(&header)) {
336 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
338 TPS65217_LDO_VOLTAGE_OUT_3_3,
340 puts("tps65217_reg_write failure\n");
342 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
344 TPS65217_LDO_VOLTAGE_OUT_1_8,
346 puts("tps65217_reg_write failure\n");
349 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
351 TPS65217_LDO_VOLTAGE_OUT_3_3,
353 puts("tps65217_reg_write failure\n");
358 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
359 * MPU frequencies we support we use a CORE voltage of
360 * 1.1375V. For MPU voltage we need to switch based on
361 * the frequency we are running at.
363 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
367 * Depending on MPU clock and PG we will need a different
368 * VDD to drive at that speed.
370 sil_rev = readl(&cdev->deviceid) >> 28;
371 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
374 /* Tell the TPS65910 to use i2c */
375 tps65910_set_i2c_control();
377 /* First update MPU voltage. */
378 if (tps65910_voltage_update(MPU, mpu_vdd))
381 /* Second, update the CORE voltage. */
382 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
385 /* Set CORE Frequencies to OPP100 */
386 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
389 /* Set MPU Frequency to what we detected now that voltages are set */
390 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
393 const struct dpll_params *get_dpll_ddr_params(void)
395 struct am335x_baseboard_id header;
397 enable_i2c0_pin_mux();
398 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
399 if (read_eeprom(&header) < 0)
400 puts("Could not get board ID.\n");
402 if (board_is_evm_sk(&header))
403 return &dpll_ddr_evm_sk;
404 else if (board_is_bone_lt(&header))
405 return &dpll_ddr_bone_black;
406 else if (board_is_evm_15_or_later(&header))
407 return &dpll_ddr_evm_sk;
412 void set_uart_mux_conf(void)
414 #ifdef CONFIG_SERIAL1
415 enable_uart0_pin_mux();
416 #endif /* CONFIG_SERIAL1 */
417 #ifdef CONFIG_SERIAL2
418 enable_uart1_pin_mux();
419 #endif /* CONFIG_SERIAL2 */
420 #ifdef CONFIG_SERIAL3
421 enable_uart2_pin_mux();
422 #endif /* CONFIG_SERIAL3 */
423 #ifdef CONFIG_SERIAL4
424 enable_uart3_pin_mux();
425 #endif /* CONFIG_SERIAL4 */
426 #ifdef CONFIG_SERIAL5
427 enable_uart4_pin_mux();
428 #endif /* CONFIG_SERIAL5 */
429 #ifdef CONFIG_SERIAL6
430 enable_uart5_pin_mux();
431 #endif /* CONFIG_SERIAL6 */
434 void set_mux_conf_regs(void)
436 __maybe_unused struct am335x_baseboard_id header;
438 if (read_eeprom(&header) < 0)
439 puts("Could not get board ID.\n");
441 enable_board_pin_mux(&header);
444 void sdram_init(void)
446 __maybe_unused struct am335x_baseboard_id header;
448 if (read_eeprom(&header) < 0)
449 puts("Could not get board ID.\n");
451 if (board_is_evm_sk(&header)) {
453 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
454 * This is safe enough to do on older revs.
456 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
457 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
460 if (board_is_evm_sk(&header))
461 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
462 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
463 else if (board_is_bone_lt(&header))
464 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
465 &ddr3_beagleblack_data,
466 &ddr3_beagleblack_cmd_ctrl_data,
467 &ddr3_beagleblack_emif_reg_data, 0);
468 else if (board_is_evm_15_or_later(&header))
469 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
470 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
472 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
473 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
478 * Basic board specific setup. Pinmux has been handled already.
483 const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
484 STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
485 STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
488 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
493 /* Reconfigure CS0 for NOR instead of NAND. */
494 enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
495 CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
501 #ifdef CONFIG_BOARD_LATE_INIT
502 int board_late_init(void)
504 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
505 char safe_string[HDR_NAME_LEN + 1];
506 struct am335x_baseboard_id header;
508 if (read_eeprom(&header) < 0)
509 puts("Could not get board ID.\n");
511 /* Now set variables based on the header. */
512 strncpy(safe_string, (char *)header.name, sizeof(header.name));
513 safe_string[sizeof(header.name)] = 0;
514 setenv("board_name", safe_string);
516 strncpy(safe_string, (char *)header.version, sizeof(header.version));
517 safe_string[sizeof(header.version)] = 0;
518 setenv("board_rev", safe_string);
525 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
526 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
527 static void cpsw_control(int enabled)
529 /* VTP can be added here */
534 static struct cpsw_slave_data cpsw_slaves[] = {
536 .slave_reg_ofs = 0x208,
537 .sliver_reg_ofs = 0xd80,
541 .slave_reg_ofs = 0x308,
542 .sliver_reg_ofs = 0xdc0,
547 static struct cpsw_platform_data cpsw_data = {
548 .mdio_base = CPSW_MDIO_BASE,
549 .cpsw_base = CPSW_BASE,
552 .cpdma_reg_ofs = 0x800,
554 .slave_data = cpsw_slaves,
555 .ale_reg_ofs = 0xd00,
557 .host_port_reg_ofs = 0x108,
558 .hw_stats_reg_ofs = 0x900,
559 .bd_ram_ofs = 0x2000,
560 .mac_control = (1 << 5),
561 .control = cpsw_control,
563 .version = CPSW_CTRL_VERSION_2,
567 #if defined(CONFIG_DRIVER_TI_CPSW) || \
568 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
569 int board_eth_init(bd_t *bis)
573 uint32_t mac_hi, mac_lo;
574 __maybe_unused struct am335x_baseboard_id header;
576 /* try reading mac address from efuse */
577 mac_lo = readl(&cdev->macid0l);
578 mac_hi = readl(&cdev->macid0h);
579 mac_addr[0] = mac_hi & 0xFF;
580 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
581 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
582 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
583 mac_addr[4] = mac_lo & 0xFF;
584 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
586 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
587 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
588 if (!getenv("ethaddr")) {
589 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
591 if (is_valid_ether_addr(mac_addr))
592 eth_setenv_enetaddr("ethaddr", mac_addr);
595 #ifdef CONFIG_DRIVER_TI_CPSW
596 if (read_eeprom(&header) < 0)
597 puts("Could not get board ID.\n");
599 if (board_is_bone(&header) || board_is_bone_lt(&header) ||
600 board_is_idk(&header)) {
601 writel(MII_MODE_ENABLE, &cdev->miisel);
602 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
603 PHY_INTERFACE_MODE_MII;
605 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
606 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
607 PHY_INTERFACE_MODE_RGMII;
610 rv = cpsw_register(&cpsw_data);
612 printf("Error %d registering CPSW switch\n", rv);
619 * CPSW RGMII Internal Delay Mode is not supported in all PVT
620 * operating points. So we must set the TX clock delay feature
621 * in the AR8051 PHY. Since we only support a single ethernet
622 * device in U-Boot, we only do this for the first instance.
624 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
625 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
626 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
627 #define AR8051_RGMII_TX_CLK_DLY 0x100
629 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
631 devname = miiphy_get_current_dev();
633 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
634 AR8051_DEBUG_RGMII_CLK_DLY_REG);
635 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
636 AR8051_RGMII_TX_CLK_DLY);
639 #if defined(CONFIG_USB_ETHER) && \
640 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
641 if (is_valid_ether_addr(mac_addr))
642 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
644 rv = usb_eth_initialize(bis);
646 printf("Error %d registering USB_ETHER\n", rv);