4 * Board functions for TI AM335X based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
34 /* MII mode defines */
35 #define MII_MODE_ENABLE 0x0
36 #define RGMII_MODE_ENABLE 0x3A
38 /* GPIO that controls power to DDR on EVM-SK */
39 #define GPIO_DDR_VTT_EN 7
41 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
43 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
45 static inline int board_is_bone(void)
47 return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
50 static inline int board_is_bone_lt(void)
52 return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
55 static inline int board_is_evm_sk(void)
57 return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
60 static inline int board_is_idk(void)
62 return !strncmp(header.config, "SKU#02", 6);
65 static int __maybe_unused board_is_gp_evm(void)
67 return !strncmp("A33515BB", header.name, 8);
70 int board_is_evm_15_or_later(void)
72 return (!strncmp("A33515BB", header.name, 8) &&
73 strncmp("1.5", header.version, 3) <= 0);
77 * Read header information from EEPROM into global structure.
79 static int read_eeprom(void)
81 /* Check if baseboard eeprom is available */
82 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
83 puts("Could not probe the EEPROM; something fundamentally "
84 "wrong on the I2C bus.\n");
88 /* read the eeprom using i2c */
89 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
91 puts("Could not read the EEPROM; something fundamentally"
92 " wrong on the I2C bus.\n");
96 if (header.magic != 0xEE3355AA) {
98 * read the eeprom using i2c again,
99 * but use only a 1 byte address
101 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
102 (uchar *)&header, sizeof(header))) {
103 puts("Could not read the EEPROM; something "
104 "fundamentally wrong on the I2C bus.\n");
108 if (header.magic != 0xEE3355AA) {
109 printf("Incorrect magic number (0x%x) in EEPROM\n",
118 #ifdef CONFIG_SPL_BUILD
119 static const struct ddr_data ddr2_data = {
120 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
121 (MT47H128M16RT25E_RD_DQS<<20) |
122 (MT47H128M16RT25E_RD_DQS<<10) |
123 (MT47H128M16RT25E_RD_DQS<<0)),
124 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
125 (MT47H128M16RT25E_WR_DQS<<20) |
126 (MT47H128M16RT25E_WR_DQS<<10) |
127 (MT47H128M16RT25E_WR_DQS<<0)),
128 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
129 (MT47H128M16RT25E_PHY_WRLVL<<20) |
130 (MT47H128M16RT25E_PHY_WRLVL<<10) |
131 (MT47H128M16RT25E_PHY_WRLVL<<0)),
132 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
133 (MT47H128M16RT25E_PHY_GATELVL<<20) |
134 (MT47H128M16RT25E_PHY_GATELVL<<10) |
135 (MT47H128M16RT25E_PHY_GATELVL<<0)),
136 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
137 (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
138 (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
139 (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
140 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
141 (MT47H128M16RT25E_PHY_WR_DATA<<20) |
142 (MT47H128M16RT25E_PHY_WR_DATA<<10) |
143 (MT47H128M16RT25E_PHY_WR_DATA<<0)),
144 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
145 .datadldiff0 = PHY_DLL_LOCK_DIFF,
148 static const struct cmd_control ddr2_cmd_ctrl_data = {
149 .cmd0csratio = MT47H128M16RT25E_RATIO,
150 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
151 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
153 .cmd1csratio = MT47H128M16RT25E_RATIO,
154 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
155 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
157 .cmd2csratio = MT47H128M16RT25E_RATIO,
158 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
159 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
162 static const struct emif_regs ddr2_emif_reg_data = {
163 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
164 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
165 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
166 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
167 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
168 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
171 static const struct ddr_data ddr3_data = {
172 .datardsratio0 = MT41J128MJT125_RD_DQS,
173 .datawdsratio0 = MT41J128MJT125_WR_DQS,
174 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
175 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
176 .datadldiff0 = PHY_DLL_LOCK_DIFF,
179 static const struct ddr_data ddr3_beagleblack_data = {
180 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
181 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
182 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
183 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
184 .datadldiff0 = PHY_DLL_LOCK_DIFF,
187 static const struct ddr_data ddr3_evm_data = {
188 .datardsratio0 = MT41J512M8RH125_RD_DQS,
189 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
190 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
191 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
192 .datadldiff0 = PHY_DLL_LOCK_DIFF,
195 static const struct cmd_control ddr3_cmd_ctrl_data = {
196 .cmd0csratio = MT41J128MJT125_RATIO,
197 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
198 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
200 .cmd1csratio = MT41J128MJT125_RATIO,
201 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
202 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
204 .cmd2csratio = MT41J128MJT125_RATIO,
205 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
206 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
209 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
210 .cmd0csratio = MT41K256M16HA125E_RATIO,
211 .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
212 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
214 .cmd1csratio = MT41K256M16HA125E_RATIO,
215 .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
216 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
218 .cmd2csratio = MT41K256M16HA125E_RATIO,
219 .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
220 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
223 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
224 .cmd0csratio = MT41J512M8RH125_RATIO,
225 .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
226 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
228 .cmd1csratio = MT41J512M8RH125_RATIO,
229 .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
230 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
232 .cmd2csratio = MT41J512M8RH125_RATIO,
233 .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
234 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
237 static struct emif_regs ddr3_emif_reg_data = {
238 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
239 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
240 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
241 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
242 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
243 .zq_config = MT41J128MJT125_ZQ_CFG,
244 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
248 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
249 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
250 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
251 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
252 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
253 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
254 .zq_config = MT41K256M16HA125E_ZQ_CFG,
255 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
258 static struct emif_regs ddr3_evm_emif_reg_data = {
259 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
260 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
261 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
262 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
263 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
264 .zq_config = MT41J512M8RH125_ZQ_CFG,
265 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
269 #ifdef CONFIG_SPL_OS_BOOT
270 int spl_start_uboot(void)
272 /* break into full u-boot on 'c' */
273 return (serial_tstc() && serial_getc() == 'c');
280 * early system init of muxing and clocks.
285 * Save the boot parameters passed from romcode.
286 * We cannot delay the saving further than this,
287 * to prevent overwrites.
289 #ifdef CONFIG_SPL_BUILD
290 save_omap_boot_params();
293 /* WDT1 is already running when the bootloader gets control
294 * Disable it to avoid "random" resets
296 writel(0xAAAA, &wdtimer->wdtwspr);
297 while (readl(&wdtimer->wdtwwps) != 0x0)
299 writel(0x5555, &wdtimer->wdtwspr);
300 while (readl(&wdtimer->wdtwwps) != 0x0)
303 #ifdef CONFIG_SPL_BUILD
304 /* Setup the PLLs and the clocks for the peripherals */
307 /* Enable RTC32K clock */
310 #ifdef CONFIG_SERIAL1
311 enable_uart0_pin_mux();
312 #endif /* CONFIG_SERIAL1 */
313 #ifdef CONFIG_SERIAL2
314 enable_uart1_pin_mux();
315 #endif /* CONFIG_SERIAL2 */
316 #ifdef CONFIG_SERIAL3
317 enable_uart2_pin_mux();
318 #endif /* CONFIG_SERIAL3 */
319 #ifdef CONFIG_SERIAL4
320 enable_uart3_pin_mux();
321 #endif /* CONFIG_SERIAL4 */
322 #ifdef CONFIG_SERIAL5
323 enable_uart4_pin_mux();
324 #endif /* CONFIG_SERIAL5 */
325 #ifdef CONFIG_SERIAL6
326 enable_uart5_pin_mux();
327 #endif /* CONFIG_SERIAL6 */
333 preloader_console_init();
335 /* Initalize the board header */
336 enable_i2c0_pin_mux();
337 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
338 if (read_eeprom() < 0)
339 puts("Could not get board ID.\n");
341 enable_board_pin_mux(&header);
342 if (board_is_evm_sk()) {
344 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
345 * This is safe enough to do on older revs.
347 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
348 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
351 if (board_is_evm_sk())
352 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
353 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
354 else if (board_is_bone_lt())
355 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
356 &ddr3_beagleblack_data,
357 &ddr3_beagleblack_cmd_ctrl_data,
358 &ddr3_beagleblack_emif_reg_data, 0);
359 else if (board_is_evm_15_or_later())
360 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
361 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
363 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
364 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
369 * Basic board specific setup. Pinmux has been handled already.
373 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
374 if (read_eeprom() < 0)
375 puts("Could not get board ID.\n");
377 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
384 #ifdef CONFIG_BOARD_LATE_INIT
385 int board_late_init(void)
387 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
388 char safe_string[HDR_NAME_LEN + 1];
390 /* Now set variables based on the header. */
391 strncpy(safe_string, (char *)header.name, sizeof(header.name));
392 safe_string[sizeof(header.name)] = 0;
393 setenv("board_name", safe_string);
395 strncpy(safe_string, (char *)header.version, sizeof(header.version));
396 safe_string[sizeof(header.version)] = 0;
397 setenv("board_rev", safe_string);
404 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
405 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
406 static void cpsw_control(int enabled)
408 /* VTP can be added here */
413 static struct cpsw_slave_data cpsw_slaves[] = {
415 .slave_reg_ofs = 0x208,
416 .sliver_reg_ofs = 0xd80,
420 .slave_reg_ofs = 0x308,
421 .sliver_reg_ofs = 0xdc0,
426 static struct cpsw_platform_data cpsw_data = {
427 .mdio_base = CPSW_MDIO_BASE,
428 .cpsw_base = CPSW_BASE,
431 .cpdma_reg_ofs = 0x800,
433 .slave_data = cpsw_slaves,
434 .ale_reg_ofs = 0xd00,
436 .host_port_reg_ofs = 0x108,
437 .hw_stats_reg_ofs = 0x900,
438 .mac_control = (1 << 5),
439 .control = cpsw_control,
441 .version = CPSW_CTRL_VERSION_2,
445 #if defined(CONFIG_DRIVER_TI_CPSW) || \
446 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
447 int board_eth_init(bd_t *bis)
451 uint32_t mac_hi, mac_lo;
453 /* try reading mac address from efuse */
454 mac_lo = readl(&cdev->macid0l);
455 mac_hi = readl(&cdev->macid0h);
456 mac_addr[0] = mac_hi & 0xFF;
457 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
458 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
459 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
460 mac_addr[4] = mac_lo & 0xFF;
461 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
463 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
464 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
465 if (!getenv("ethaddr")) {
466 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
468 if (is_valid_ether_addr(mac_addr))
469 eth_setenv_enetaddr("ethaddr", mac_addr);
472 #ifdef CONFIG_DRIVER_TI_CPSW
473 if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
474 writel(MII_MODE_ENABLE, &cdev->miisel);
475 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
476 PHY_INTERFACE_MODE_MII;
478 writel(RGMII_MODE_ENABLE, &cdev->miisel);
479 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
480 PHY_INTERFACE_MODE_RGMII;
483 rv = cpsw_register(&cpsw_data);
485 printf("Error %d registering CPSW switch\n", rv);
492 * CPSW RGMII Internal Delay Mode is not supported in all PVT
493 * operating points. So we must set the TX clock delay feature
494 * in the AR8051 PHY. Since we only support a single ethernet
495 * device in U-Boot, we only do this for the first instance.
497 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
498 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
499 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
500 #define AR8051_RGMII_TX_CLK_DLY 0x100
502 if (board_is_evm_sk() || board_is_gp_evm()) {
504 devname = miiphy_get_current_dev();
506 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
507 AR8051_DEBUG_RGMII_CLK_DLY_REG);
508 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
509 AR8051_RGMII_TX_CLK_DLY);
512 #if defined(CONFIG_USB_ETHER) && \
513 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
514 if (is_valid_ether_addr(mac_addr))
515 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
517 rv = usb_eth_initialize(bis);
519 printf("Error %d registering USB_ETHER\n", rv);