4 * Board functions for TI AM335X based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
29 #include <power/tps65217.h>
30 #include <power/tps65910.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 /* GPIO that controls power to DDR on EVM-SK */
36 #define GPIO_DDR_VTT_EN 7
38 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
41 * Read header information from EEPROM into global structure.
43 static int read_eeprom(struct am335x_baseboard_id *header)
45 /* Check if baseboard eeprom is available */
46 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
47 puts("Could not probe the EEPROM; something fundamentally "
48 "wrong on the I2C bus.\n");
52 /* read the eeprom using i2c */
53 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
54 sizeof(struct am335x_baseboard_id))) {
55 puts("Could not read the EEPROM; something fundamentally"
56 " wrong on the I2C bus.\n");
60 if (header->magic != 0xEE3355AA) {
62 * read the eeprom using i2c again,
63 * but use only a 1 byte address
65 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
66 sizeof(struct am335x_baseboard_id))) {
67 puts("Could not read the EEPROM; something "
68 "fundamentally wrong on the I2C bus.\n");
72 if (header->magic != 0xEE3355AA) {
73 printf("Incorrect magic number (0x%x) in EEPROM\n",
82 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
83 static const struct ddr_data ddr2_data = {
84 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
85 (MT47H128M16RT25E_RD_DQS<<20) |
86 (MT47H128M16RT25E_RD_DQS<<10) |
87 (MT47H128M16RT25E_RD_DQS<<0)),
88 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
89 (MT47H128M16RT25E_WR_DQS<<20) |
90 (MT47H128M16RT25E_WR_DQS<<10) |
91 (MT47H128M16RT25E_WR_DQS<<0)),
92 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
93 (MT47H128M16RT25E_PHY_WRLVL<<20) |
94 (MT47H128M16RT25E_PHY_WRLVL<<10) |
95 (MT47H128M16RT25E_PHY_WRLVL<<0)),
96 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
97 (MT47H128M16RT25E_PHY_GATELVL<<20) |
98 (MT47H128M16RT25E_PHY_GATELVL<<10) |
99 (MT47H128M16RT25E_PHY_GATELVL<<0)),
100 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
101 (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
102 (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
103 (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
104 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
105 (MT47H128M16RT25E_PHY_WR_DATA<<20) |
106 (MT47H128M16RT25E_PHY_WR_DATA<<10) |
107 (MT47H128M16RT25E_PHY_WR_DATA<<0)),
108 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
109 .datadldiff0 = PHY_DLL_LOCK_DIFF,
112 static const struct cmd_control ddr2_cmd_ctrl_data = {
113 .cmd0csratio = MT47H128M16RT25E_RATIO,
114 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
115 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
117 .cmd1csratio = MT47H128M16RT25E_RATIO,
118 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
119 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
121 .cmd2csratio = MT47H128M16RT25E_RATIO,
122 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
123 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
126 static const struct emif_regs ddr2_emif_reg_data = {
127 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
128 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
129 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
130 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
131 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
132 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
135 static const struct ddr_data ddr3_data = {
136 .datardsratio0 = MT41J128MJT125_RD_DQS,
137 .datawdsratio0 = MT41J128MJT125_WR_DQS,
138 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
139 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
140 .datadldiff0 = PHY_DLL_LOCK_DIFF,
143 static const struct ddr_data ddr3_beagleblack_data = {
144 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
145 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
146 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
147 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
148 .datadldiff0 = PHY_DLL_LOCK_DIFF,
151 static const struct ddr_data ddr3_evm_data = {
152 .datardsratio0 = MT41J512M8RH125_RD_DQS,
153 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
154 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
155 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
156 .datadldiff0 = PHY_DLL_LOCK_DIFF,
159 static const struct cmd_control ddr3_cmd_ctrl_data = {
160 .cmd0csratio = MT41J128MJT125_RATIO,
161 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
162 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
164 .cmd1csratio = MT41J128MJT125_RATIO,
165 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
166 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
168 .cmd2csratio = MT41J128MJT125_RATIO,
169 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
170 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
173 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
174 .cmd0csratio = MT41K256M16HA125E_RATIO,
175 .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
176 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
178 .cmd1csratio = MT41K256M16HA125E_RATIO,
179 .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
180 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
182 .cmd2csratio = MT41K256M16HA125E_RATIO,
183 .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
184 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
187 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
188 .cmd0csratio = MT41J512M8RH125_RATIO,
189 .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
190 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
192 .cmd1csratio = MT41J512M8RH125_RATIO,
193 .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
194 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
196 .cmd2csratio = MT41J512M8RH125_RATIO,
197 .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
198 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
201 static struct emif_regs ddr3_emif_reg_data = {
202 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
203 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
204 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
205 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
206 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
207 .zq_config = MT41J128MJT125_ZQ_CFG,
208 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
212 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
213 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
214 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
215 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
216 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
217 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
218 .zq_config = MT41K256M16HA125E_ZQ_CFG,
219 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
222 static struct emif_regs ddr3_evm_emif_reg_data = {
223 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
224 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
225 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
226 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
227 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
228 .zq_config = MT41J512M8RH125_ZQ_CFG,
229 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
233 #ifdef CONFIG_SPL_OS_BOOT
234 int spl_start_uboot(void)
236 /* break into full u-boot on 'c' */
237 return (serial_tstc() && serial_getc() == 'c');
241 #define OSC (V_OSCK/1000000)
242 const struct dpll_params dpll_ddr = {
243 266, OSC-1, 1, -1, -1, -1, -1};
244 const struct dpll_params dpll_ddr_evm_sk = {
245 303, OSC-1, 1, -1, -1, -1, -1};
246 const struct dpll_params dpll_ddr_bone_black = {
247 400, OSC-1, 1, -1, -1, -1, -1};
249 void am33xx_spl_board_init(void)
251 struct am335x_baseboard_id header;
252 struct dpll_params dpll_mpu = {0, OSC-1, 1, -1, -1, -1, -1};
255 if (read_eeprom(&header) < 0)
256 puts("Could not get board ID.\n");
258 /* Get the frequency */
259 dpll_mpu.m = am335x_get_efuse_mpu_max_freq(cdev);
261 if (board_is_bone(&header) || board_is_bone_lt(&header)) {
262 /* BeagleBone PMIC Code */
266 * Only perform PMIC configurations if board rev > A1
267 * on Beaglebone White
269 if (board_is_bone(&header) && !strncmp(header.version,
273 if (i2c_probe(TPS65217_CHIP_PM))
277 * On Beaglebone White we need to ensure we have AC power
278 * before increasing the frequency.
280 if (board_is_bone(&header)) {
281 uchar pmic_status_reg;
282 if (tps65217_reg_read(TPS65217_STATUS,
285 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
286 puts("No AC power, disabling frequency switch\n");
292 * Override what we have detected since we know if we have
293 * a Beaglebone Black it supports 1GHz.
295 if (board_is_bone_lt(&header))
296 dpll_mpu.m = MPUPLL_M_1000;
299 * Increase USB current limit to 1300mA or 1800mA and set
300 * the MPU voltage controller as needed.
302 if (dpll_mpu.m == MPUPLL_M_1000) {
303 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
304 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
306 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
307 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
310 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
313 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
314 puts("tps65217_reg_write failure\n");
317 /* Set DCDC2 (MPU) voltage */
318 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
319 puts("tps65217_voltage_update failure\n");
324 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
325 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
327 if (board_is_bone(&header)) {
328 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
330 TPS65217_LDO_VOLTAGE_OUT_3_3,
332 puts("tps65217_reg_write failure\n");
334 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
336 TPS65217_LDO_VOLTAGE_OUT_1_8,
338 puts("tps65217_reg_write failure\n");
341 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
343 TPS65217_LDO_VOLTAGE_OUT_3_3,
345 puts("tps65217_reg_write failure\n");
350 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
351 * MPU frequencies we support we use a CORE voltage of
352 * 1.1375V. For MPU voltage we need to switch based on
353 * the frequency we are running at.
355 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
359 * Depending on MPU clock and PG we will need a different
360 * VDD to drive at that speed.
362 sil_rev = readl(&cdev->deviceid) >> 28;
363 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, dpll_mpu.m);
365 /* Tell the TPS65910 to use i2c */
366 tps65910_set_i2c_control();
368 /* First update MPU voltage. */
369 if (tps65910_voltage_update(MPU, mpu_vdd))
372 /* Second, update the CORE voltage. */
373 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
377 /* Set MPU Frequency to what we detected now that voltages are set */
378 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
381 const struct dpll_params *get_dpll_ddr_params(void)
383 struct am335x_baseboard_id header;
385 enable_i2c0_pin_mux();
386 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
387 if (read_eeprom(&header) < 0)
388 puts("Could not get board ID.\n");
390 if (board_is_evm_sk(&header))
391 return &dpll_ddr_evm_sk;
392 else if (board_is_bone_lt(&header))
393 return &dpll_ddr_bone_black;
394 else if (board_is_evm_15_or_later(&header))
395 return &dpll_ddr_evm_sk;
400 void set_uart_mux_conf(void)
402 #ifdef CONFIG_SERIAL1
403 enable_uart0_pin_mux();
404 #endif /* CONFIG_SERIAL1 */
405 #ifdef CONFIG_SERIAL2
406 enable_uart1_pin_mux();
407 #endif /* CONFIG_SERIAL2 */
408 #ifdef CONFIG_SERIAL3
409 enable_uart2_pin_mux();
410 #endif /* CONFIG_SERIAL3 */
411 #ifdef CONFIG_SERIAL4
412 enable_uart3_pin_mux();
413 #endif /* CONFIG_SERIAL4 */
414 #ifdef CONFIG_SERIAL5
415 enable_uart4_pin_mux();
416 #endif /* CONFIG_SERIAL5 */
417 #ifdef CONFIG_SERIAL6
418 enable_uart5_pin_mux();
419 #endif /* CONFIG_SERIAL6 */
422 void set_mux_conf_regs(void)
424 __maybe_unused struct am335x_baseboard_id header;
426 if (read_eeprom(&header) < 0)
427 puts("Could not get board ID.\n");
429 enable_board_pin_mux(&header);
432 void sdram_init(void)
434 __maybe_unused struct am335x_baseboard_id header;
436 if (read_eeprom(&header) < 0)
437 puts("Could not get board ID.\n");
439 if (board_is_evm_sk(&header)) {
441 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
442 * This is safe enough to do on older revs.
444 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
445 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
448 if (board_is_evm_sk(&header))
449 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
450 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
451 else if (board_is_bone_lt(&header))
452 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
453 &ddr3_beagleblack_data,
454 &ddr3_beagleblack_cmd_ctrl_data,
455 &ddr3_beagleblack_emif_reg_data, 0);
456 else if (board_is_evm_15_or_later(&header))
457 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
458 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
460 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
461 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
466 * Basic board specific setup. Pinmux has been handled already.
471 const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
472 STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
473 STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
476 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
481 /* Reconfigure CS0 for NOR instead of NAND. */
482 enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
483 CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
489 #ifdef CONFIG_BOARD_LATE_INIT
490 int board_late_init(void)
492 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
493 char safe_string[HDR_NAME_LEN + 1];
494 struct am335x_baseboard_id header;
496 if (read_eeprom(&header) < 0)
497 puts("Could not get board ID.\n");
499 /* Now set variables based on the header. */
500 strncpy(safe_string, (char *)header.name, sizeof(header.name));
501 safe_string[sizeof(header.name)] = 0;
502 setenv("board_name", safe_string);
504 strncpy(safe_string, (char *)header.version, sizeof(header.version));
505 safe_string[sizeof(header.version)] = 0;
506 setenv("board_rev", safe_string);
513 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
514 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
515 static void cpsw_control(int enabled)
517 /* VTP can be added here */
522 static struct cpsw_slave_data cpsw_slaves[] = {
524 .slave_reg_ofs = 0x208,
525 .sliver_reg_ofs = 0xd80,
529 .slave_reg_ofs = 0x308,
530 .sliver_reg_ofs = 0xdc0,
535 static struct cpsw_platform_data cpsw_data = {
536 .mdio_base = CPSW_MDIO_BASE,
537 .cpsw_base = CPSW_BASE,
540 .cpdma_reg_ofs = 0x800,
542 .slave_data = cpsw_slaves,
543 .ale_reg_ofs = 0xd00,
545 .host_port_reg_ofs = 0x108,
546 .hw_stats_reg_ofs = 0x900,
547 .bd_ram_ofs = 0x2000,
548 .mac_control = (1 << 5),
549 .control = cpsw_control,
551 .version = CPSW_CTRL_VERSION_2,
555 #if defined(CONFIG_DRIVER_TI_CPSW) || \
556 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
557 int board_eth_init(bd_t *bis)
561 uint32_t mac_hi, mac_lo;
562 __maybe_unused struct am335x_baseboard_id header;
564 /* try reading mac address from efuse */
565 mac_lo = readl(&cdev->macid0l);
566 mac_hi = readl(&cdev->macid0h);
567 mac_addr[0] = mac_hi & 0xFF;
568 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
569 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
570 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
571 mac_addr[4] = mac_lo & 0xFF;
572 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
574 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
575 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
576 if (!getenv("ethaddr")) {
577 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
579 if (is_valid_ether_addr(mac_addr))
580 eth_setenv_enetaddr("ethaddr", mac_addr);
583 #ifdef CONFIG_DRIVER_TI_CPSW
584 if (read_eeprom(&header) < 0)
585 puts("Could not get board ID.\n");
587 if (board_is_bone(&header) || board_is_bone_lt(&header) ||
588 board_is_idk(&header)) {
589 writel(MII_MODE_ENABLE, &cdev->miisel);
590 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
591 PHY_INTERFACE_MODE_MII;
593 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
594 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
595 PHY_INTERFACE_MODE_RGMII;
598 rv = cpsw_register(&cpsw_data);
600 printf("Error %d registering CPSW switch\n", rv);
607 * CPSW RGMII Internal Delay Mode is not supported in all PVT
608 * operating points. So we must set the TX clock delay feature
609 * in the AR8051 PHY. Since we only support a single ethernet
610 * device in U-Boot, we only do this for the first instance.
612 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
613 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
614 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
615 #define AR8051_RGMII_TX_CLK_DLY 0x100
617 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
619 devname = miiphy_get_current_dev();
621 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
622 AR8051_DEBUG_RGMII_CLK_DLY_REG);
623 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
624 AR8051_RGMII_TX_CLK_DLY);
627 #if defined(CONFIG_USB_ETHER) && \
628 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
629 if (is_valid_ether_addr(mac_addr))
630 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
632 rv = usb_eth_initialize(bis);
634 printf("Error %d registering USB_ETHER\n", rv);