git.sur5r.net Git - u-boot/blob - board/ti/am335x/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <spl.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/omap.h>
  17 #include <asm/arch/ddr_defs.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/mmc_host_def.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mem.h>
  23 #include <asm/io.h>
  24 #include <asm/emif.h>
  25 #include <asm/gpio.h>
  26 #include <i2c.h>
  27 #include <miiphy.h>
  28 #include <cpsw.h>
  29 #include "board.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  34
  35 /* MII mode defines */
  36 #define MII_MODE_ENABLE         0x0
  37 #define RGMII_MODE_ENABLE       0x3A
  38
  39 /* GPIO that controls power to DDR on EVM-SK */
  40 #define GPIO_DDR_VTT_EN         7
  41
  42 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  43
  44 /*
  45  * Read header information from EEPROM into global structure.
  46  */
  47 static int read_eeprom(struct am335x_baseboard_id *header)
  48 {
  49         /* Check if baseboard eeprom is available */
  50         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  51                 puts("Could not probe the EEPROM; something fundamentally "
  52                         "wrong on the I2C bus.\n");
  53                 return -ENODEV;
  54         }
  55
  56         /* read the eeprom using i2c */
  57         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  58                      sizeof(struct am335x_baseboard_id))) {
  59                 puts("Could not read the EEPROM; something fundamentally"
  60                         " wrong on the I2C bus.\n");
  61                 return -EIO;
  62         }
  63
  64         if (header->magic != 0xEE3355AA) {
  65                 /*
  66                  * read the eeprom using i2c again,
  67                  * but use only a 1 byte address
  68                  */
  69                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  70                              sizeof(struct am335x_baseboard_id))) {
  71                         puts("Could not read the EEPROM; something "
  72                                 "fundamentally wrong on the I2C bus.\n");
  73                         return -EIO;
  74                 }
  75
  76                 if (header->magic != 0xEE3355AA) {
  77                         printf("Incorrect magic number (0x%x) in EEPROM\n",
  78                                         header->magic);
  79                         return -EINVAL;
  80                 }
  81         }
  82
  83         return 0;
  84 }
  85
  86 #ifdef CONFIG_SPL_BUILD
  87 static const struct ddr_data ddr2_data = {
  88         .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
  89                           (MT47H128M16RT25E_RD_DQS<<20) |
  90                           (MT47H128M16RT25E_RD_DQS<<10) |
  91                           (MT47H128M16RT25E_RD_DQS<<0)),
  92         .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
  93                           (MT47H128M16RT25E_WR_DQS<<20) |
  94                           (MT47H128M16RT25E_WR_DQS<<10) |
  95                           (MT47H128M16RT25E_WR_DQS<<0)),
  96         .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
  97                          (MT47H128M16RT25E_PHY_WRLVL<<20) |
  98                          (MT47H128M16RT25E_PHY_WRLVL<<10) |
  99                          (MT47H128M16RT25E_PHY_WRLVL<<0)),
 100         .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
 101                          (MT47H128M16RT25E_PHY_GATELVL<<20) |
 102                          (MT47H128M16RT25E_PHY_GATELVL<<10) |
 103                          (MT47H128M16RT25E_PHY_GATELVL<<0)),
 104         .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
 105                           (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
 106                           (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
 107                           (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
 108         .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
 109                           (MT47H128M16RT25E_PHY_WR_DATA<<20) |
 110                           (MT47H128M16RT25E_PHY_WR_DATA<<10) |
 111                           (MT47H128M16RT25E_PHY_WR_DATA<<0)),
 112         .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
 113         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 114 };
 115
 116 static const struct cmd_control ddr2_cmd_ctrl_data = {
 117         .cmd0csratio = MT47H128M16RT25E_RATIO,
 118         .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 119         .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 120
 121         .cmd1csratio = MT47H128M16RT25E_RATIO,
 122         .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 123         .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 124
 125         .cmd2csratio = MT47H128M16RT25E_RATIO,
 126         .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 127         .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 128 };
 129
 130 static const struct emif_regs ddr2_emif_reg_data = {
 131         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 132         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 133         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 134         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 135         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 136         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 137 };
 138
 139 static const struct ddr_data ddr3_data = {
 140         .datardsratio0 = MT41J128MJT125_RD_DQS,
 141         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 142         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 143         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 144         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 145 };
 146
 147 static const struct ddr_data ddr3_beagleblack_data = {
 148         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 149         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 150         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 151         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 152         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 153 };
 154
 155 static const struct ddr_data ddr3_evm_data = {
 156         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 157         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 158         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 159         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 160         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 161 };
 162
 163 static const struct cmd_control ddr3_cmd_ctrl_data = {
 164         .cmd0csratio = MT41J128MJT125_RATIO,
 165         .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 166         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 167
 168         .cmd1csratio = MT41J128MJT125_RATIO,
 169         .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 170         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 171
 172         .cmd2csratio = MT41J128MJT125_RATIO,
 173         .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 174         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 175 };
 176
 177 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 178         .cmd0csratio = MT41K256M16HA125E_RATIO,
 179         .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 180         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 181
 182         .cmd1csratio = MT41K256M16HA125E_RATIO,
 183         .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 184         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 185
 186         .cmd2csratio = MT41K256M16HA125E_RATIO,
 187         .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 188         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 189 };
 190
 191 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 192         .cmd0csratio = MT41J512M8RH125_RATIO,
 193         .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 194         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 195
 196         .cmd1csratio = MT41J512M8RH125_RATIO,
 197         .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 198         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 199
 200         .cmd2csratio = MT41J512M8RH125_RATIO,
 201         .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 202         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 203 };
 204
 205 static struct emif_regs ddr3_emif_reg_data = {
 206         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 207         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 208         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 209         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 210         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 211         .zq_config = MT41J128MJT125_ZQ_CFG,
 212         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 213                                 PHY_EN_DYN_PWRDN,
 214 };
 215
 216 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 217         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 218         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 219         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 220         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 221         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 222         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 223         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 224 };
 225
 226 static struct emif_regs ddr3_evm_emif_reg_data = {
 227         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 228         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 229         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 230         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 231         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 232         .zq_config = MT41J512M8RH125_ZQ_CFG,
 233         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 234                                 PHY_EN_DYN_PWRDN,
 235 };
 236
 237 #ifdef CONFIG_SPL_OS_BOOT
 238 int spl_start_uboot(void)
 239 {
 240         /* break into full u-boot on 'c' */
 241         return (serial_tstc() && serial_getc() == 'c');
 242 }
 243 #endif
 244
 245 #endif
 246
 247 /*
 248  * early system init of muxing and clocks.
 249  */
 250 void s_init(void)
 251 {
 252 #ifdef CONFIG_SPL_BUILD
 253         struct am335x_baseboard_id header;
 254
 255         /*
 256          * Save the boot parameters passed from romcode.
 257          * We cannot delay the saving further than this,
 258          * to prevent overwrites.
 259          */
 260         save_omap_boot_params();
 261 #endif
 262
 263         /* WDT1 is already running when the bootloader gets control
 264          * Disable it to avoid "random" resets
 265          */
 266         writel(0xAAAA, &wdtimer->wdtwspr);
 267         while (readl(&wdtimer->wdtwwps) != 0x0)
 268                 ;
 269         writel(0x5555, &wdtimer->wdtwspr);
 270         while (readl(&wdtimer->wdtwwps) != 0x0)
 271                 ;
 272
 273 #ifdef CONFIG_SPL_BUILD
 274         /* Setup the PLLs and the clocks for the peripherals */
 275         pll_init();
 276
 277         /* Enable RTC32K clock */
 278         rtc32k_enable();
 279
 280 #ifdef CONFIG_SERIAL1
 281         enable_uart0_pin_mux();
 282 #endif /* CONFIG_SERIAL1 */
 283 #ifdef CONFIG_SERIAL2
 284         enable_uart1_pin_mux();
 285 #endif /* CONFIG_SERIAL2 */
 286 #ifdef CONFIG_SERIAL3
 287         enable_uart2_pin_mux();
 288 #endif /* CONFIG_SERIAL3 */
 289 #ifdef CONFIG_SERIAL4
 290         enable_uart3_pin_mux();
 291 #endif /* CONFIG_SERIAL4 */
 292 #ifdef CONFIG_SERIAL5
 293         enable_uart4_pin_mux();
 294 #endif /* CONFIG_SERIAL5 */
 295 #ifdef CONFIG_SERIAL6
 296         enable_uart5_pin_mux();
 297 #endif /* CONFIG_SERIAL6 */
 298
 299         uart_soft_reset();
 300
 301         gd = &gdata;
 302
 303         preloader_console_init();
 304
 305         /* Initalize the board header */
 306         enable_i2c0_pin_mux();
 307         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 308         if (read_eeprom(&header) < 0)
 309                 puts("Could not get board ID.\n");
 310
 311         enable_board_pin_mux(&header);
 312         if (board_is_evm_sk(&header)) {
 313                 /*
 314                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 315                  * This is safe enough to do on older revs.
 316                  */
 317                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 318                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 319         }
 320
 321         if (board_is_evm_sk(&header))
 322                 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
 323                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 324         else if (board_is_bone_lt(&header))
 325                 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
 326                            &ddr3_beagleblack_data,
 327                            &ddr3_beagleblack_cmd_ctrl_data,
 328                            &ddr3_beagleblack_emif_reg_data, 0);
 329         else if (board_is_evm_15_or_later(&header))
 330                 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
 331                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 332         else
 333                 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
 334                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 335 #endif
 336 }
 337
 338 /*
 339  * Basic board specific setup.  Pinmux has been handled already.
 340  */
 341 int board_init(void)
 342 {
 343 #ifdef CONFIG_NOR
 344         const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
 345                 STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
 346                 STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
 347 #endif
 348
 349         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 350
 351         gpmc_init();
 352
 353 #ifdef CONFIG_NOR
 354         /* Reconfigure CS0 for NOR instead of NAND. */
 355         enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
 356                               CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
 357 #endif
 358
 359         return 0;
 360 }
 361
 362 #ifdef CONFIG_BOARD_LATE_INIT
 363 int board_late_init(void)
 364 {
 365 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 366         char safe_string[HDR_NAME_LEN + 1];
 367         struct am335x_baseboard_id header;
 368
 369         if (read_eeprom(&header) < 0)
 370                 puts("Could not get board ID.\n");
 371
 372         /* Now set variables based on the header. */
 373         strncpy(safe_string, (char *)header.name, sizeof(header.name));
 374         safe_string[sizeof(header.name)] = 0;
 375         setenv("board_name", safe_string);
 376
 377         strncpy(safe_string, (char *)header.version, sizeof(header.version));
 378         safe_string[sizeof(header.version)] = 0;
 379         setenv("board_rev", safe_string);
 380 #endif
 381
 382         return 0;
 383 }
 384 #endif
 385
 386 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 387         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 388 static void cpsw_control(int enabled)
 389 {
 390         /* VTP can be added here */
 391
 392         return;
 393 }
 394
 395 static struct cpsw_slave_data cpsw_slaves[] = {
 396         {
 397                 .slave_reg_ofs  = 0x208,
 398                 .sliver_reg_ofs = 0xd80,
 399                 .phy_id         = 0,
 400         },
 401         {
 402                 .slave_reg_ofs  = 0x308,
 403                 .sliver_reg_ofs = 0xdc0,
 404                 .phy_id         = 1,
 405         },
 406 };
 407
 408 static struct cpsw_platform_data cpsw_data = {
 409         .mdio_base              = CPSW_MDIO_BASE,
 410         .cpsw_base              = CPSW_BASE,
 411         .mdio_div               = 0xff,
 412         .channels               = 8,
 413         .cpdma_reg_ofs          = 0x800,
 414         .slaves                 = 1,
 415         .slave_data             = cpsw_slaves,
 416         .ale_reg_ofs            = 0xd00,
 417         .ale_entries            = 1024,
 418         .host_port_reg_ofs      = 0x108,
 419         .hw_stats_reg_ofs       = 0x900,
 420         .bd_ram_ofs             = 0x2000,
 421         .mac_control            = (1 << 5),
 422         .control                = cpsw_control,
 423         .host_port_num          = 0,
 424         .version                = CPSW_CTRL_VERSION_2,
 425 };
 426 #endif
 427
 428 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 429         (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
 430 int board_eth_init(bd_t *bis)
 431 {
 432         int rv, n = 0;
 433         uint8_t mac_addr[6];
 434         uint32_t mac_hi, mac_lo;
 435         __maybe_unused struct am335x_baseboard_id header;
 436
 437         /* try reading mac address from efuse */
 438         mac_lo = readl(&cdev->macid0l);
 439         mac_hi = readl(&cdev->macid0h);
 440         mac_addr[0] = mac_hi & 0xFF;
 441         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 442         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 443         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 444         mac_addr[4] = mac_lo & 0xFF;
 445         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 446
 447 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 448         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 449         if (!getenv("ethaddr")) {
 450                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 451
 452                 if (is_valid_ether_addr(mac_addr))
 453                         eth_setenv_enetaddr("ethaddr", mac_addr);
 454         }
 455
 456 #ifdef CONFIG_DRIVER_TI_CPSW
 457         if (read_eeprom(&header) < 0)
 458                 puts("Could not get board ID.\n");
 459
 460         if (board_is_bone(&header) || board_is_bone_lt(&header) ||
 461             board_is_idk(&header)) {
 462                 writel(MII_MODE_ENABLE, &cdev->miisel);
 463                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 464                                 PHY_INTERFACE_MODE_MII;
 465         } else {
 466                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 467                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 468                                 PHY_INTERFACE_MODE_RGMII;
 469         }
 470
 471         rv = cpsw_register(&cpsw_data);
 472         if (rv < 0)
 473                 printf("Error %d registering CPSW switch\n", rv);
 474         else
 475                 n += rv;
 476 #endif
 477
 478         /*
 479          *
 480          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 481          * operating points.  So we must set the TX clock delay feature
 482          * in the AR8051 PHY.  Since we only support a single ethernet
 483          * device in U-Boot, we only do this for the first instance.
 484          */
 485 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 486 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 487 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 488 #define AR8051_RGMII_TX_CLK_DLY         0x100
 489
 490         if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
 491                 const char *devname;
 492                 devname = miiphy_get_current_dev();
 493
 494                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 495                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
 496                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 497                                 AR8051_RGMII_TX_CLK_DLY);
 498         }
 499 #endif
 500 #if defined(CONFIG_USB_ETHER) && \
 501         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 502         if (is_valid_ether_addr(mac_addr))
 503                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 504
 505         rv = usb_eth_initialize(bis);
 506         if (rv < 0)
 507                 printf("Error %d registering USB_ETHER\n", rv);
 508         else
 509                 n += rv;
 510 #endif
 511         return n;
 512 }
 513 #endif