4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/mux.h>
22 #include "../common/board_detect.h"
25 static struct module_pin_mux uart0_pin_mux[] = {
26 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
31 static struct module_pin_mux uart1_pin_mux[] = {
32 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
33 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
37 static struct module_pin_mux uart2_pin_mux[] = {
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
39 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
43 static struct module_pin_mux uart3_pin_mux[] = {
44 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
45 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
49 static struct module_pin_mux uart4_pin_mux[] = {
50 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
51 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
55 static struct module_pin_mux uart5_pin_mux[] = {
56 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
57 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
61 static struct module_pin_mux mmc0_pin_mux[] = {
62 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
63 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
64 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
65 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
66 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
67 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
68 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
69 {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */
73 static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
74 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
75 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
76 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
77 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
78 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
79 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
80 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
84 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
85 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
86 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
87 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
88 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
89 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
90 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
91 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
95 static struct module_pin_mux mmc1_pin_mux[] = {
96 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
97 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
98 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
99 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
100 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
101 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
102 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
103 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
107 static struct module_pin_mux i2c0_pin_mux[] = {
108 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
109 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
110 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
111 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
115 static struct module_pin_mux i2c1_pin_mux[] = {
116 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
117 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
118 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
119 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
123 static struct module_pin_mux spi0_pin_mux[] = {
124 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
125 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
126 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
127 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
128 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
129 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
133 static struct module_pin_mux gpio0_7_pin_mux[] = {
134 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
138 static struct module_pin_mux rgmii1_pin_mux[] = {
139 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
140 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
141 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
142 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
143 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
144 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
145 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
146 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
147 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
148 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
149 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
150 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
151 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
152 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
156 static struct module_pin_mux mii1_pin_mux[] = {
157 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
158 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
159 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
160 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
161 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
162 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
163 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
164 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
165 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
166 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
167 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
168 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
169 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
170 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
171 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
176 static struct module_pin_mux nand_pin_mux[] = {
177 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
178 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
179 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
180 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
181 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
182 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
183 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
184 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
185 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
186 {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
187 {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
188 {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
189 {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
190 {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
191 {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
192 {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
193 {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
195 {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
196 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
197 {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
198 {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
199 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
200 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
201 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
204 #elif defined(CONFIG_NOR)
205 static struct module_pin_mux bone_norcape_pin_mux[] = {
206 {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
207 {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
208 {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
209 {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
210 {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
211 {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
212 {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
213 {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
214 {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
215 {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
216 {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
217 {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
218 {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
219 {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
220 {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
221 {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
222 {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
223 {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
224 {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
225 {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
226 {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
227 {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
228 {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
229 {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
230 {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
231 {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
232 {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
233 {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
234 {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
235 {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
240 #if defined(CONFIG_NOR_BOOT)
241 void enable_norboot_pin_mux(void)
243 configure_module_pin_mux(bone_norcape_pin_mux);
247 void enable_uart0_pin_mux(void)
249 configure_module_pin_mux(uart0_pin_mux);
252 void enable_uart1_pin_mux(void)
254 configure_module_pin_mux(uart1_pin_mux);
257 void enable_uart2_pin_mux(void)
259 configure_module_pin_mux(uart2_pin_mux);
262 void enable_uart3_pin_mux(void)
264 configure_module_pin_mux(uart3_pin_mux);
267 void enable_uart4_pin_mux(void)
269 configure_module_pin_mux(uart4_pin_mux);
272 void enable_uart5_pin_mux(void)
274 configure_module_pin_mux(uart5_pin_mux);
277 void enable_i2c0_pin_mux(void)
279 configure_module_pin_mux(i2c0_pin_mux);
283 * The AM335x GP EVM, if daughter card(s) are connected, can have 8
284 * different profiles. These profiles determine what peripherals are
285 * valid and need pinmux to be configured.
287 #define PROFILE_NONE 0x0
288 #define PROFILE_0 (1 << 0)
289 #define PROFILE_1 (1 << 1)
290 #define PROFILE_2 (1 << 2)
291 #define PROFILE_3 (1 << 3)
292 #define PROFILE_4 (1 << 4)
293 #define PROFILE_5 (1 << 5)
294 #define PROFILE_6 (1 << 6)
295 #define PROFILE_7 (1 << 7)
296 #define PROFILE_MASK 0x7
297 #define PROFILE_ALL 0xFF
300 #define I2C_CPLD_ADDR 0x35
303 static unsigned short detect_daughter_board_profile(void)
307 if (i2c_probe(I2C_CPLD_ADDR))
310 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
313 return (1 << (val & PROFILE_MASK));
316 void enable_board_pin_mux(void)
318 /* Do board-specific muxes. */
319 if (board_is_bone()) {
320 /* Beaglebone pinmux */
321 configure_module_pin_mux(mii1_pin_mux);
322 configure_module_pin_mux(mmc0_pin_mux);
323 #if defined(CONFIG_NAND)
324 configure_module_pin_mux(nand_pin_mux);
325 #elif defined(CONFIG_NOR)
326 configure_module_pin_mux(bone_norcape_pin_mux);
328 configure_module_pin_mux(mmc1_pin_mux);
330 } else if (board_is_gp_evm()) {
331 /* General Purpose EVM */
332 unsigned short profile = detect_daughter_board_profile();
333 configure_module_pin_mux(rgmii1_pin_mux);
334 configure_module_pin_mux(mmc0_pin_mux);
335 /* In profile #2 i2c1 and spi0 conflict. */
336 if (profile & ~PROFILE_2)
337 configure_module_pin_mux(i2c1_pin_mux);
338 /* Profiles 2 & 3 don't have NAND */
340 if (profile & ~(PROFILE_2 | PROFILE_3))
341 configure_module_pin_mux(nand_pin_mux);
343 else if (profile == PROFILE_2) {
344 configure_module_pin_mux(mmc1_pin_mux);
345 configure_module_pin_mux(spi0_pin_mux);
347 } else if (board_is_idk()) {
348 /* Industrial Motor Control (IDK) */
349 configure_module_pin_mux(mii1_pin_mux);
350 configure_module_pin_mux(mmc0_no_cd_pin_mux);
351 } else if (board_is_evm_sk()) {
352 /* Starter Kit EVM */
353 configure_module_pin_mux(i2c1_pin_mux);
354 configure_module_pin_mux(gpio0_7_pin_mux);
355 configure_module_pin_mux(rgmii1_pin_mux);
356 configure_module_pin_mux(mmc0_pin_mux_sk_evm);
357 } else if (board_is_bone_lt()) {
358 /* Beaglebone LT pinmux */
359 configure_module_pin_mux(mii1_pin_mux);
360 configure_module_pin_mux(mmc0_pin_mux);
361 #if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
362 configure_module_pin_mux(nand_pin_mux);
363 #elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
364 configure_module_pin_mux(bone_norcape_pin_mux);
366 configure_module_pin_mux(mmc1_pin_mux);
369 puts("Unknown board, cannot configure pinmux.");