4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <asm/arch/common_def.h>
18 #include <asm/arch/hardware.h>
21 #define MUX_CFG(value, offset) \
22 __raw_writel(value, (CTRL_BASE + offset));
24 /* PAD Control Fields */
25 #define SLEWCTRL (0x1 << 6)
26 #define RXACTIVE (0x1 << 5)
27 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
28 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
29 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
30 #define MODE(val) val /* used for Readability */
34 * Field names corresponds to the pad signal name
126 int ecap0_in_pwm0_out;
145 int xdma_event_intr0;
146 int xdma_event_intr1;
245 struct module_pin_mux {
250 /* Pad control register offset */
251 #define PAD_CTRL_BASE 0x800
252 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
255 static struct module_pin_mux uart0_pin_mux[] = {
256 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
257 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
262 static struct module_pin_mux mmc0_pin_mux[] = {
263 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
264 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
265 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
266 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
267 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
268 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
269 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
270 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
275 static struct module_pin_mux i2c0_pin_mux[] = {
276 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
277 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
278 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
279 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
283 static struct module_pin_mux i2c1_pin_mux[] = {
284 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
285 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
286 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
287 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
291 static struct module_pin_mux gpio0_7_pin_mux[] = {
292 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
296 static struct module_pin_mux rgmii1_pin_mux[] = {
297 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
298 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
299 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
300 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
301 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
302 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
303 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
304 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
305 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
306 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
307 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
308 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
309 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
310 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
314 static struct module_pin_mux mii1_pin_mux[] = {
315 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
316 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
317 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
318 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
319 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
320 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
321 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
322 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
323 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
324 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
325 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
326 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
327 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
328 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
329 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
334 * Configure the pin mux for the module
336 static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
343 for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
344 MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
347 void enable_uart0_pin_mux(void)
349 configure_module_pin_mux(uart0_pin_mux);
353 void enable_mmc0_pin_mux(void)
355 configure_module_pin_mux(mmc0_pin_mux);
359 void enable_i2c0_pin_mux(void)
361 configure_module_pin_mux(i2c0_pin_mux);
364 void enable_i2c1_pin_mux(void)
366 configure_module_pin_mux(i2c1_pin_mux);
369 void enable_rgmii1_pin_mux(void)
371 configure_module_pin_mux(rgmii1_pin_mux);
374 void enable_mii1_pin_mux(void)
376 configure_module_pin_mux(mii1_pin_mux);
379 void enable_gpio0_7_pin_mux(void)
381 configure_module_pin_mux(gpio0_7_pin_mux);