4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/hardware.h>
22 #define MUX_CFG(value, offset) \
23 __raw_writel(value, (CTRL_BASE + offset));
25 /* PAD Control Fields */
26 #define SLEWCTRL (0x1 << 6)
27 #define RXACTIVE (0x1 << 5)
28 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
29 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
30 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
31 #define MODE(val) val /* used for Readability */
35 * Field names corresponds to the pad signal name
127 int ecap0_in_pwm0_out;
146 int xdma_event_intr0;
147 int xdma_event_intr1;
246 struct module_pin_mux {
251 /* Pad control register offset */
252 #define PAD_CTRL_BASE 0x800
253 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
256 static struct module_pin_mux uart0_pin_mux[] = {
257 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
258 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
262 static struct module_pin_mux mmc0_pin_mux[] = {
263 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
264 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
265 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
266 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
267 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
268 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
269 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
270 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
274 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
275 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
276 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
277 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
278 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
279 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
280 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
281 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
285 static struct module_pin_mux mmc1_pin_mux[] = {
286 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
287 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
288 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
289 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
290 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
291 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
292 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
293 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
297 static struct module_pin_mux i2c0_pin_mux[] = {
298 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
299 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
300 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
301 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
305 static struct module_pin_mux i2c1_pin_mux[] = {
306 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
307 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
308 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
309 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
313 static struct module_pin_mux gpio0_7_pin_mux[] = {
314 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
318 static struct module_pin_mux rgmii1_pin_mux[] = {
319 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
320 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
321 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
322 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
323 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
324 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
325 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
326 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
327 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
328 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
329 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
330 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
331 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
332 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
336 static struct module_pin_mux mii1_pin_mux[] = {
337 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
338 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
339 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
340 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
341 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
342 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
343 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
344 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
345 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
346 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
347 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
348 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
349 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
350 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
351 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
356 * Configure the pin mux for the module
358 static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
365 for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
366 MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
369 void enable_uart0_pin_mux(void)
371 configure_module_pin_mux(uart0_pin_mux);
375 void enable_i2c0_pin_mux(void)
377 configure_module_pin_mux(i2c0_pin_mux);
381 * The AM335x GP EVM, if daughter card(s) are connected, can have 8
382 * different profiles. These profiles determine what peripherals are
383 * valid and need pinmux to be configured.
385 #define PROFILE_NONE 0x0
386 #define PROFILE_0 (1 << 0)
387 #define PROFILE_1 (1 << 1)
388 #define PROFILE_2 (1 << 2)
389 #define PROFILE_3 (1 << 3)
390 #define PROFILE_4 (1 << 4)
391 #define PROFILE_5 (1 << 5)
392 #define PROFILE_6 (1 << 6)
393 #define PROFILE_7 (1 << 7)
394 #define PROFILE_MASK 0x7
395 #define PROFILE_ALL 0xFF
398 #define I2C_CPLD_ADDR 0x35
401 static unsigned short detect_daughter_board_profile(void)
405 if (i2c_probe(I2C_CPLD_ADDR))
408 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
411 return (1 << (val & PROFILE_MASK));
414 void enable_board_pin_mux(struct am335x_baseboard_id *header)
416 /* Do board-specific muxes. */
417 if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) {
418 /* Beaglebone pinmux */
419 configure_module_pin_mux(i2c1_pin_mux);
420 configure_module_pin_mux(mii1_pin_mux);
421 configure_module_pin_mux(mmc0_pin_mux);
422 configure_module_pin_mux(mmc1_pin_mux);
423 } else if (!strncmp(header->config, "SKU#01", 6)) {
424 /* General Purpose EVM */
425 unsigned short profile = detect_daughter_board_profile();
426 configure_module_pin_mux(rgmii1_pin_mux);
427 configure_module_pin_mux(mmc0_pin_mux);
428 /* In profile #2 i2c1 and spi0 conflict. */
429 if (profile & ~PROFILE_2)
430 configure_module_pin_mux(i2c1_pin_mux);
431 else if (profile == PROFILE_2) {
432 configure_module_pin_mux(mmc1_pin_mux);
434 } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
435 /* Starter Kit EVM */
436 configure_module_pin_mux(i2c1_pin_mux);
437 configure_module_pin_mux(gpio0_7_pin_mux);
438 configure_module_pin_mux(rgmii1_pin_mux);
439 configure_module_pin_mux(mmc0_pin_mux_sk_evm);
441 puts("Unknown board, cannot configure pinmux.");