git.sur5r.net Git - u-boot/blob - board/ti/am43xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM43XX based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <i2c.h>
  13 #include <asm/errno.h>
  14 #include <spl.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/arch/mux.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/emif.h>
  21 #include "board.h"
  22 #include <power/pmic.h>
  23 #include <power/tps65218.h>
  24 #include <miiphy.h>
  25 #include <cpsw.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  30
  31 /*
  32  * Read header information from EEPROM into global structure.
  33  */
  34 static int read_eeprom(struct am43xx_board_id *header)
  35 {
  36         /* Check if baseboard eeprom is available */
  37         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  38                 printf("Could not probe the EEPROM at 0x%x\n",
  39                        CONFIG_SYS_I2C_EEPROM_ADDR);
  40                 return -ENODEV;
  41         }
  42
  43         /* read the eeprom using i2c */
  44         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  45                      sizeof(struct am43xx_board_id))) {
  46                 printf("Could not read the EEPROM\n");
  47                 return -EIO;
  48         }
  49
  50         if (header->magic != 0xEE3355AA) {
  51                 /*
  52                  * read the eeprom using i2c again,
  53                  * but use only a 1 byte address
  54                  */
  55                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  56                              sizeof(struct am43xx_board_id))) {
  57                         printf("Could not read the EEPROM at 0x%x\n",
  58                                CONFIG_SYS_I2C_EEPROM_ADDR);
  59                         return -EIO;
  60                 }
  61
  62                 if (header->magic != 0xEE3355AA) {
  63                         printf("Incorrect magic number (0x%x) in EEPROM\n",
  64                                header->magic);
  65                         return -EINVAL;
  66                 }
  67         }
  68
  69         strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
  70         am43xx_board_name[sizeof(header->name)] = 0;
  71
  72         strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
  73         am43xx_board_rev[sizeof(header->version)] = 0;
  74
  75         return 0;
  76 }
  77
  78 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  79
  80 #define NUM_OPPS        6
  81
  82 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  83         {       /* 19.2 MHz */
  84                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  85                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  86                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  87                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  88                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  89                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  90         },
  91         {       /* 24 MHz */
  92                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  93                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  94                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  95                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  96                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  97                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  98         },
  99         {       /* 25 MHz */
 100                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
 101                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
 102                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
 103                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
 104                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
 105                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
 106         },
 107         {       /* 26 MHz */
 108                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
 109                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
 110                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
 111                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
 112                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
 113                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
 114         },
 115 };
 116
 117 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
 118                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
 119                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
 120                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
 121                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
 122 };
 123
 124 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
 125                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
 126                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
 127                 {384, 9, 5, -1, -1, -1, -1},    /* 25 MHz */
 128                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
 129 };
 130
 131 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 132                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 133                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 134                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 135                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 136 };
 137
 138 const struct dpll_params gp_evm_dpll_ddr = {
 139                 50, 2, 1, -1, 2, -1, -1};
 140
 141 const struct ctrl_ioregs ioregs_lpddr2 = {
 142         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 143         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 144         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 145         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 146         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 147         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 148         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 149         .emif_sdram_config_ext  = 0x1,
 150 };
 151
 152 const struct emif_regs emif_regs_lpddr2 = {
 153         .sdram_config                   = 0x808012BA,
 154         .ref_ctrl                       = 0x0000040D,
 155         .sdram_tim1                     = 0xEA86B411,
 156         .sdram_tim2                     = 0x103A094A,
 157         .sdram_tim3                     = 0x0F6BA37F,
 158         .read_idle_ctrl                 = 0x00050000,
 159         .zq_config                      = 0x50074BE4,
 160         .temp_alert_config              = 0x0,
 161         .emif_rd_wr_lvl_rmp_win         = 0x0,
 162         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 163         .emif_rd_wr_lvl_ctl             = 0x0,
 164         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 165         .emif_rd_wr_exec_thresh         = 0x80000405,
 166         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 167         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 168         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 169         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 170         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 171         .emif_prio_class_serv_map       = 0x80000001,
 172         .emif_connect_id_serv_1_map     = 0x80000094,
 173         .emif_connect_id_serv_2_map     = 0x00000000,
 174         .emif_cos_config                        = 0x000FFFFF
 175 };
 176
 177 const struct ctrl_ioregs ioregs_ddr3 = {
 178         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 179         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 180         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 181         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 182         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 183         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 184         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 185         .emif_sdram_config_ext  = 0xc163,
 186 };
 187
 188 const struct emif_regs ddr3_emif_regs_400Mhz = {
 189         .sdram_config                   = 0x638413B2,
 190         .ref_ctrl                       = 0x00000C30,
 191         .sdram_tim1                     = 0xEAAAD4DB,
 192         .sdram_tim2                     = 0x266B7FDA,
 193         .sdram_tim3                     = 0x107F8678,
 194         .read_idle_ctrl                 = 0x00050000,
 195         .zq_config                      = 0x50074BE4,
 196         .temp_alert_config              = 0x0,
 197         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 198         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 199         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 200         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 201         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 202         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 203         .emif_rd_wr_lvl_rmp_win         = 0x0,
 204         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 205         .emif_rd_wr_lvl_ctl             = 0x0,
 206         .emif_rd_wr_exec_thresh         = 0x80000405,
 207         .emif_prio_class_serv_map       = 0x80000001,
 208         .emif_connect_id_serv_1_map     = 0x80000094,
 209         .emif_connect_id_serv_2_map     = 0x00000000,
 210         .emif_cos_config                = 0x000FFFFF
 211 };
 212
 213 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 214 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 215         .sdram_config                   = 0x638413B2,
 216         .ref_ctrl                       = 0x00000C30,
 217         .sdram_tim1                     = 0xEAAAD4DB,
 218         .sdram_tim2                     = 0x266B7FDA,
 219         .sdram_tim3                     = 0x107F8678,
 220         .read_idle_ctrl                 = 0x00050000,
 221         .zq_config                      = 0x50074BE4,
 222         .temp_alert_config              = 0x0,
 223         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 224         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 225         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 226         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 227         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 228         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 229         .emif_rd_wr_exec_thresh         = 0x80000405,
 230         .emif_prio_class_serv_map       = 0x80000001,
 231         .emif_connect_id_serv_1_map     = 0x80000094,
 232         .emif_connect_id_serv_2_map     = 0x00000000,
 233         .emif_cos_config                = 0x000FFFFF
 234 };
 235
 236 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 237 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 238         .sdram_config                   = 0x638413B2,
 239         .ref_ctrl                       = 0x00000C30,
 240         .sdram_tim1                     = 0xEAAAD4DB,
 241         .sdram_tim2                     = 0x266B7FDA,
 242         .sdram_tim3                     = 0x107F8678,
 243         .read_idle_ctrl                 = 0x00050000,
 244         .zq_config                      = 0x50074BE4,
 245         .temp_alert_config              = 0x0,
 246         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 247         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 248         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 249         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 250         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 251         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 252         .emif_rd_wr_exec_thresh         = 0x80000405,
 253         .emif_prio_class_serv_map       = 0x80000001,
 254         .emif_connect_id_serv_1_map     = 0x80000094,
 255         .emif_connect_id_serv_2_map     = 0x00000000,
 256         .emif_cos_config                = 0x000FFFFF
 257 };
 258
 259 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 260         .sdram_config                   = 0x638413b2,
 261         .sdram_config2                  = 0x00000000,
 262         .ref_ctrl                       = 0x00000c30,
 263         .sdram_tim1                     = 0xeaaad4db,
 264         .sdram_tim2                     = 0x266b7fda,
 265         .sdram_tim3                     = 0x107f8678,
 266         .read_idle_ctrl                 = 0x00050000,
 267         .zq_config                      = 0x50074be4,
 268         .temp_alert_config              = 0x0,
 269         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 270         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 271         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 272         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 273         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 274         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 275         .emif_rd_wr_lvl_rmp_win         = 0x0,
 276         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 277         .emif_rd_wr_lvl_ctl             = 0x00000000,
 278         .emif_rd_wr_exec_thresh         = 0x80000000,
 279         .emif_prio_class_serv_map       = 0x80000001,
 280         .emif_connect_id_serv_1_map     = 0x80000094,
 281         .emif_connect_id_serv_2_map     = 0x00000000,
 282         .emif_cos_config                = 0x000FFFFF
 283 };
 284
 285 /*
 286  * get_sys_clk_index : returns the index of the sys_clk read from
 287  *                      ctrl status register. This value is either
 288  *                      read from efuse or sysboot pins.
 289  */
 290 static u32 get_sys_clk_index(void)
 291 {
 292         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 293         u32 ind = readl(&ctrl->statusreg), src;
 294
 295         src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
 296         if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
 297                 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
 298                         CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
 299         else /* Value read from SYS BOOT pins */
 300                 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
 301                         CTRL_SYSBOOT_15_14_SHIFT);
 302 }
 303
 304 const struct dpll_params *get_dpll_ddr_params(void)
 305 {
 306         int ind = get_sys_clk_index();
 307
 308         if (board_is_eposevm())
 309                 return &epos_evm_dpll_ddr[ind];
 310         else if (board_is_gpevm() || board_is_sk())
 311                 return &gp_evm_dpll_ddr;
 312
 313         printf(" Board '%s' not supported\n", am43xx_board_name);
 314         return NULL;
 315 }
 316
 317
 318 /*
 319  * get_opp_offset:
 320  * Returns the index for safest OPP of the device to boot.
 321  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 322  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 323  * This data is read from dev_attribute register which is e-fused.
 324  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 325  * OPP available. Lowest OPP starts with min_off. So returning the
 326  * bit with rightmost '0'.
 327  */
 328 static int get_opp_offset(int max_off, int min_off)
 329 {
 330         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 331         int opp, offset, i;
 332
 333         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 334         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 335
 336         for (i = max_off; i >= min_off; i--) {
 337                 offset = opp & (1 << i);
 338                 if (!offset)
 339                         return i;
 340         }
 341
 342         return min_off;
 343 }
 344
 345 const struct dpll_params *get_dpll_mpu_params(void)
 346 {
 347         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 348         u32 ind = get_sys_clk_index();
 349
 350         return &dpll_mpu[ind][opp];
 351 }
 352
 353 const struct dpll_params *get_dpll_core_params(void)
 354 {
 355         int ind = get_sys_clk_index();
 356
 357         return &dpll_core[ind];
 358 }
 359
 360 const struct dpll_params *get_dpll_per_params(void)
 361 {
 362         int ind = get_sys_clk_index();
 363
 364         return &dpll_per[ind];
 365 }
 366
 367 void scale_vcores(void)
 368 {
 369         const struct dpll_params *mpu_params;
 370         int mpu_vdd;
 371         struct am43xx_board_id header;
 372
 373         enable_i2c0_pin_mux();
 374         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 375         if (read_eeprom(&header) < 0)
 376                 puts("Could not get board ID.\n");
 377
 378         /* Get the frequency */
 379         mpu_params = get_dpll_mpu_params();
 380
 381         if (i2c_probe(TPS65218_CHIP_PM))
 382                 return;
 383
 384         switch (mpu_params->m) {
 385         case 1000:
 386                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 387                 break;
 388         case 800:
 389                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
 390                 break;
 391         case 720:
 392                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
 393                 break;
 394         case 600:
 395                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 396                 break;
 397         case 300:
 398                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
 399                 break;
 400         default:
 401                 puts("Unknown MPU clock, not scaling\n");
 402                 return;
 403         }
 404
 405         /* Set DCDC1 (CORE) voltage to 1.1V */
 406         if (tps65218_voltage_update(TPS65218_DCDC1,
 407                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 408                 puts("tps65218_voltage_update failure\n");
 409                 return;
 410         }
 411
 412         /* Set DCDC2 (MPU) voltage */
 413         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 414                 puts("tps65218_voltage_update failure\n");
 415                 return;
 416         }
 417 }
 418
 419 void set_uart_mux_conf(void)
 420 {
 421         enable_uart0_pin_mux();
 422 }
 423
 424 void set_mux_conf_regs(void)
 425 {
 426         enable_board_pin_mux();
 427 }
 428
 429 static void enable_vtt_regulator(void)
 430 {
 431         u32 temp;
 432
 433         /* enable module */
 434         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 435
 436         /* enable output for GPIO5_7 */
 437         writel(GPIO_SETDATAOUT(7),
 438                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 439         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 440         temp = temp & ~(GPIO_OE_ENABLE(7));
 441         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 442 }
 443
 444 void sdram_init(void)
 445 {
 446         /*
 447          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 448          * GP EMV has 1GB DDR3 connected to EMIF
 449          * along with VTT regulator.
 450          */
 451         if (board_is_eposevm()) {
 452                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 453         } else if (board_is_evm_14_or_later()) {
 454                 enable_vtt_regulator();
 455                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 456                            &ddr3_emif_regs_400Mhz_production, 0);
 457         } else if (board_is_evm_12_or_later()) {
 458                 enable_vtt_regulator();
 459                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 460                            &ddr3_emif_regs_400Mhz_beta, 0);
 461         } else if (board_is_gpevm()) {
 462                 enable_vtt_regulator();
 463                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 464                            &ddr3_emif_regs_400Mhz, 0);
 465         } else if (board_is_sk()) {
 466                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 467                            &ddr3_sk_emif_regs_400Mhz, 0);
 468         }
 469 }
 470 #endif
 471
 472 /* setup board specific PMIC */
 473 int power_init_board(void)
 474 {
 475         struct pmic *p;
 476
 477         power_tps65218_init(I2C_PMIC);
 478         p = pmic_get("TPS65218_PMIC");
 479         if (p && !pmic_probe(p))
 480                 puts("PMIC:  TPS65218\n");
 481
 482         return 0;
 483 }
 484
 485 int board_init(void)
 486 {
 487         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 488         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 489             modena_init0_bw_integer, modena_init0_watermark_0;
 490
 491         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 492         gpmc_init();
 493
 494         /* Clear all important bits for DSS errata that may need to be tweaked*/
 495         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 496                            MREQPRIO_0_SAB_INIT0_MASK;
 497
 498         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 499
 500         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 501                                            BW_LIMITER_BW_FRAC_MASK;
 502
 503         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 504                                         BW_LIMITER_BW_INT_MASK;
 505
 506         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 507                                          BW_LIMITER_BW_WATERMARK_MASK;
 508
 509         /* Setting MReq Priority of the DSS*/
 510         mreqprio_0 |= 0x77;
 511
 512         /*
 513          * Set L3 Fast Configuration Register
 514          * Limiting bandwith for ARM core to 700 MBPS
 515          */
 516         modena_init0_bw_fractional |= 0x10;
 517         modena_init0_bw_integer |= 0x3;
 518
 519         writel(mreqprio_0, &cdev->mreqprio_0);
 520         writel(mreqprio_1, &cdev->mreqprio_1);
 521
 522         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 523         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 524         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 525
 526         return 0;
 527 }
 528
 529 #ifdef CONFIG_BOARD_LATE_INIT
 530 int board_late_init(void)
 531 {
 532 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 533         char safe_string[HDR_NAME_LEN + 1];
 534         struct am43xx_board_id header;
 535
 536         if (read_eeprom(&header) < 0)
 537                 puts("Could not get board ID.\n");
 538
 539         /* Now set variables based on the header. */
 540         strncpy(safe_string, (char *)header.name, sizeof(header.name));
 541         safe_string[sizeof(header.name)] = 0;
 542         setenv("board_name", safe_string);
 543
 544         strncpy(safe_string, (char *)header.version, sizeof(header.version));
 545         safe_string[sizeof(header.version)] = 0;
 546         setenv("board_rev", safe_string);
 547 #endif
 548         return 0;
 549 }
 550 #endif
 551
 552 #ifdef CONFIG_DRIVER_TI_CPSW
 553
 554 static void cpsw_control(int enabled)
 555 {
 556         /* Additional controls can be added here */
 557         return;
 558 }
 559
 560 static struct cpsw_slave_data cpsw_slaves[] = {
 561         {
 562                 .slave_reg_ofs  = 0x208,
 563                 .sliver_reg_ofs = 0xd80,
 564                 .phy_addr       = 16,
 565         },
 566         {
 567                 .slave_reg_ofs  = 0x308,
 568                 .sliver_reg_ofs = 0xdc0,
 569                 .phy_addr       = 1,
 570         },
 571 };
 572
 573 static struct cpsw_platform_data cpsw_data = {
 574         .mdio_base              = CPSW_MDIO_BASE,
 575         .cpsw_base              = CPSW_BASE,
 576         .mdio_div               = 0xff,
 577         .channels               = 8,
 578         .cpdma_reg_ofs          = 0x800,
 579         .slaves                 = 1,
 580         .slave_data             = cpsw_slaves,
 581         .ale_reg_ofs            = 0xd00,
 582         .ale_entries            = 1024,
 583         .host_port_reg_ofs      = 0x108,
 584         .hw_stats_reg_ofs       = 0x900,
 585         .bd_ram_ofs             = 0x2000,
 586         .mac_control            = (1 << 5),
 587         .control                = cpsw_control,
 588         .host_port_num          = 0,
 589         .version                = CPSW_CTRL_VERSION_2,
 590 };
 591
 592 int board_eth_init(bd_t *bis)
 593 {
 594         int rv;
 595         uint8_t mac_addr[6];
 596         uint32_t mac_hi, mac_lo;
 597
 598         /* try reading mac address from efuse */
 599         mac_lo = readl(&cdev->macid0l);
 600         mac_hi = readl(&cdev->macid0h);
 601         mac_addr[0] = mac_hi & 0xFF;
 602         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 603         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 604         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 605         mac_addr[4] = mac_lo & 0xFF;
 606         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 607
 608         if (!getenv("ethaddr")) {
 609                 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 610                 if (is_valid_ether_addr(mac_addr))
 611                         eth_setenv_enetaddr("ethaddr", mac_addr);
 612         }
 613
 614         mac_lo = readl(&cdev->macid1l);
 615         mac_hi = readl(&cdev->macid1h);
 616         mac_addr[0] = mac_hi & 0xFF;
 617         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 618         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 619         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 620         mac_addr[4] = mac_lo & 0xFF;
 621         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 622
 623         if (!getenv("eth1addr")) {
 624                 if (is_valid_ether_addr(mac_addr))
 625                         eth_setenv_enetaddr("eth1addr", mac_addr);
 626         }
 627
 628         if (board_is_eposevm()) {
 629                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 630                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 631                 cpsw_slaves[0].phy_addr = 16;
 632         } else if (board_is_sk()) {
 633                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 634                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 635                 cpsw_slaves[0].phy_addr = 4;
 636                 cpsw_slaves[1].phy_addr = 5;
 637         } else {
 638                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 639                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 640                 cpsw_slaves[0].phy_addr = 0;
 641         }
 642
 643         rv = cpsw_register(&cpsw_data);
 644         if (rv < 0)
 645                 printf("Error %d registering CPSW switch\n", rv);
 646
 647         return rv;
 648 }
 649 #endif