git.sur5r.net Git - u-boot/blob - board/ti/am43xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM43XX based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <i2c.h>
  13 #include <asm/errno.h>
  14 #include <spl.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/arch/mux.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/emif.h>
  21 #include "board.h"
  22 #include <miiphy.h>
  23 #include <cpsw.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #ifndef CONFIG_SPL_BUILD
  28 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  29 #endif
  30
  31 /*
  32  * Read header information from EEPROM into global structure.
  33  */
  34 static int read_eeprom(struct am43xx_board_id *header)
  35 {
  36         /* Check if baseboard eeprom is available */
  37         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  38                 printf("Could not probe the EEPROM at 0x%x\n",
  39                        CONFIG_SYS_I2C_EEPROM_ADDR);
  40                 return -ENODEV;
  41         }
  42
  43         /* read the eeprom using i2c */
  44         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  45                      sizeof(struct am43xx_board_id))) {
  46                 printf("Could not read the EEPROM\n");
  47                 return -EIO;
  48         }
  49
  50         if (header->magic != 0xEE3355AA) {
  51                 /*
  52                  * read the eeprom using i2c again,
  53                  * but use only a 1 byte address
  54                  */
  55                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  56                              sizeof(struct am43xx_board_id))) {
  57                         printf("Could not read the EEPROM at 0x%x\n",
  58                                CONFIG_SYS_I2C_EEPROM_ADDR);
  59                         return -EIO;
  60                 }
  61
  62                 if (header->magic != 0xEE3355AA) {
  63                         printf("Incorrect magic number (0x%x) in EEPROM\n",
  64                                header->magic);
  65                         return -EINVAL;
  66                 }
  67         }
  68
  69         strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
  70         am43xx_board_name[sizeof(header->name)] = 0;
  71
  72         return 0;
  73 }
  74
  75 #ifdef CONFIG_SPL_BUILD
  76
  77 #define NUM_OPPS        6
  78
  79 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  80         {       /* 19.2 MHz */
  81                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP 50 */
  82                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  83                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP 100 */
  84                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP 120 */
  85                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP TB */
  86                 {-1, -1, -1, -1, -1, -1, -1}    /* OPP NT */
  87         },
  88         {       /* 24 MHz */
  89                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  90                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  91                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  92                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  93                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  94                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  95         },
  96         {       /* 25 MHz */
  97                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  98                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  99                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
 100                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
 101                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
 102                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
 103         },
 104         {       /* 26 MHz */
 105                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
 106                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
 107                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
 108                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
 109                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
 110                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
 111         },
 112 };
 113
 114 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
 115                 {-1, -1, -1, -1, -1, -1, -1},   /* 19.2 MHz */
 116                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
 117                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
 118                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
 119 };
 120
 121 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
 122                 {-1, -1, -1, -1, -1, -1, -1},   /* 19.2 MHz */
 123                 {960, 23, 5, -1, -1, -1, -1},   /* 24 MHz */
 124                 {960, 24, 5, -1, -1, -1, -1},   /* 25 MHz */
 125                 {960, 25, 5, -1, -1, -1, -1}    /* 26 MHz */
 126 };
 127
 128 const struct dpll_params epos_evm_dpll_ddr = {
 129                 266, 24, 1, -1, 1, -1, -1};
 130
 131 const struct dpll_params gp_evm_dpll_ddr = {
 132                 400, 23, 1, -1, 1, -1, -1};
 133
 134 const struct ctrl_ioregs ioregs_lpddr2 = {
 135         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 136         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 137         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 138         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 139         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 140         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 141         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 142         .emif_sdram_config_ext  = 0x1,
 143 };
 144
 145 const struct emif_regs emif_regs_lpddr2 = {
 146         .sdram_config                   = 0x808012BA,
 147         .ref_ctrl                       = 0x0000040D,
 148         .sdram_tim1                     = 0xEA86B411,
 149         .sdram_tim2                     = 0x103A094A,
 150         .sdram_tim3                     = 0x0F6BA37F,
 151         .read_idle_ctrl                 = 0x00050000,
 152         .zq_config                      = 0x50074BE4,
 153         .temp_alert_config              = 0x0,
 154         .emif_rd_wr_lvl_rmp_win         = 0x0,
 155         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 156         .emif_rd_wr_lvl_ctl             = 0x0,
 157         .emif_ddr_phy_ctlr_1            = 0x0E084006,
 158         .emif_rd_wr_exec_thresh         = 0x00000405,
 159         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 160         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 161         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 162         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 163         .emif_ddr_ext_phy_ctrl_5        = 0x00500050
 164 };
 165
 166 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 167         0x00500050,
 168         0x00350035,
 169         0x00350035,
 170         0x00350035,
 171         0x00350035,
 172         0x00350035,
 173         0x00000000,
 174         0x00000000,
 175         0x00000000,
 176         0x00000000,
 177         0x00000000,
 178         0x00000000,
 179         0x00000000,
 180         0x00000000,
 181         0x00000000,
 182         0x00000000,
 183         0x00000000,
 184         0x00000000,
 185         0x40001000,
 186         0x08102040
 187 };
 188
 189 const struct ctrl_ioregs ioregs_ddr3 = {
 190         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 191         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 192         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 193         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 194         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 195         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 196         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 197         .emif_sdram_config_ext  = 0x0143,
 198 };
 199
 200 const struct emif_regs ddr3_emif_regs_400Mhz = {
 201         .sdram_config                   = 0x638413B2,
 202         .ref_ctrl                       = 0x00000C30,
 203         .sdram_tim1                     = 0xEAAAD4DB,
 204         .sdram_tim2                     = 0x266B7FDA,
 205         .sdram_tim3                     = 0x107F8678,
 206         .read_idle_ctrl                 = 0x00050000,
 207         .zq_config                      = 0x50074BE4,
 208         .temp_alert_config              = 0x0,
 209         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 210         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 211         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 212         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 213         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 214         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 215         .emif_rd_wr_lvl_rmp_win         = 0x0,
 216         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 217         .emif_rd_wr_lvl_ctl             = 0x0,
 218         .emif_rd_wr_exec_thresh         = 0x00000405
 219 };
 220
 221 const u32 ext_phy_ctrl_const_base_ddr3[] = {
 222         0x00400040,
 223         0x00350035,
 224         0x00350035,
 225         0x00350035,
 226         0x00350035,
 227         0x00350035,
 228         0x00000000,
 229         0x00000000,
 230         0x00000000,
 231         0x00000000,
 232         0x00000000,
 233         0x00340034,
 234         0x00340034,
 235         0x00340034,
 236         0x00340034,
 237         0x00340034,
 238         0x0,
 239         0x0,
 240         0x40000000,
 241         0x08102040
 242 };
 243
 244 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 245 {
 246         if (board_is_eposevm()) {
 247                 *regs = ext_phy_ctrl_const_base_lpddr2;
 248                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 249         } else if (board_is_gpevm()) {
 250                 *regs = ext_phy_ctrl_const_base_ddr3;
 251                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
 252         }
 253
 254         return;
 255 }
 256
 257 const struct dpll_params *get_dpll_ddr_params(void)
 258 {
 259         struct am43xx_board_id header;
 260
 261         enable_i2c0_pin_mux();
 262         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 263         if (read_eeprom(&header) < 0)
 264                 puts("Could not get board ID.\n");
 265
 266         if (board_is_eposevm())
 267                 return &epos_evm_dpll_ddr;
 268         else if (board_is_gpevm())
 269                 return &gp_evm_dpll_ddr;
 270
 271         puts(" Board not supported\n");
 272         return NULL;
 273 }
 274
 275 /*
 276  * get_sys_clk_index : returns the index of the sys_clk read from
 277  *                      ctrl status register. This value is either
 278  *                      read from efuse or sysboot pins.
 279  */
 280 static u32 get_sys_clk_index(void)
 281 {
 282         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 283         u32 ind = readl(&ctrl->statusreg), src;
 284
 285         src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
 286         if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
 287                 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
 288                         CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
 289         else /* Value read from SYS BOOT pins */
 290                 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
 291                         CTRL_SYSBOOT_15_14_SHIFT);
 292 }
 293
 294 /*
 295  * get_opp_offset:
 296  * Returns the index for safest OPP of the device to boot.
 297  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 298  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 299  * This data is read from dev_attribute register which is e-fused.
 300  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 301  * OPP available. Lowest OPP starts with min_off. So returning the
 302  * bit with rightmost '0'.
 303  */
 304 static int get_opp_offset(int max_off, int min_off)
 305 {
 306         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 307         int opp = readl(&ctrl->dev_attr), offset, i;
 308
 309         for (i = max_off; i >= min_off; i--) {
 310                 offset = opp & (1 << i);
 311                 if (!offset)
 312                         return i;
 313         }
 314
 315         return min_off;
 316 }
 317
 318 const struct dpll_params *get_dpll_mpu_params(void)
 319 {
 320         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 321         u32 ind = get_sys_clk_index();
 322
 323         return &dpll_mpu[ind][opp];
 324 }
 325
 326 const struct dpll_params *get_dpll_core_params(void)
 327 {
 328         int ind = get_sys_clk_index();
 329
 330         return &dpll_core[ind];
 331 }
 332
 333 const struct dpll_params *get_dpll_per_params(void)
 334 {
 335         int ind = get_sys_clk_index();
 336
 337         return &dpll_per[ind];
 338 }
 339
 340 void set_uart_mux_conf(void)
 341 {
 342         enable_uart0_pin_mux();
 343 }
 344
 345 void set_mux_conf_regs(void)
 346 {
 347         enable_board_pin_mux();
 348 }
 349
 350 static void enable_vtt_regulator(void)
 351 {
 352         u32 temp;
 353
 354         /* enable module */
 355         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 356
 357         /* enable output for GPIO5_7 */
 358         writel(GPIO_SETDATAOUT(7),
 359                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 360         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 361         temp = temp & ~(GPIO_OE_ENABLE(7));
 362         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 363 }
 364
 365 void sdram_init(void)
 366 {
 367         /*
 368          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 369          * GP EMV has 1GB DDR3 connected to EMIF
 370          * along with VTT regulator.
 371          */
 372         if (board_is_eposevm()) {
 373                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 374         } else if (board_is_gpevm()) {
 375                 enable_vtt_regulator();
 376                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 377                            &ddr3_emif_regs_400Mhz, 0);
 378         }
 379 }
 380 #endif
 381
 382 int board_init(void)
 383 {
 384         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 385
 386         return 0;
 387 }
 388
 389 #ifdef CONFIG_BOARD_LATE_INIT
 390 int board_late_init(void)
 391 {
 392 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 393         char safe_string[HDR_NAME_LEN + 1];
 394         struct am43xx_board_id header;
 395
 396         if (read_eeprom(&header) < 0)
 397                 puts("Could not get board ID.\n");
 398
 399         /* Now set variables based on the header. */
 400         strncpy(safe_string, (char *)header.name, sizeof(header.name));
 401         safe_string[sizeof(header.name)] = 0;
 402         setenv("board_name", safe_string);
 403
 404         strncpy(safe_string, (char *)header.version, sizeof(header.version));
 405         safe_string[sizeof(header.version)] = 0;
 406         setenv("board_rev", safe_string);
 407 #endif
 408         return 0;
 409 }
 410 #endif
 411
 412 #ifdef CONFIG_DRIVER_TI_CPSW
 413
 414 static void cpsw_control(int enabled)
 415 {
 416         /* Additional controls can be added here */
 417         return;
 418 }
 419
 420 static struct cpsw_slave_data cpsw_slaves[] = {
 421         {
 422                 .slave_reg_ofs  = 0x208,
 423                 .sliver_reg_ofs = 0xd80,
 424                 .phy_addr       = 16,
 425         },
 426         {
 427                 .slave_reg_ofs  = 0x308,
 428                 .sliver_reg_ofs = 0xdc0,
 429                 .phy_addr       = 1,
 430         },
 431 };
 432
 433 static struct cpsw_platform_data cpsw_data = {
 434         .mdio_base              = CPSW_MDIO_BASE,
 435         .cpsw_base              = CPSW_BASE,
 436         .mdio_div               = 0xff,
 437         .channels               = 8,
 438         .cpdma_reg_ofs          = 0x800,
 439         .slaves                 = 1,
 440         .slave_data             = cpsw_slaves,
 441         .ale_reg_ofs            = 0xd00,
 442         .ale_entries            = 1024,
 443         .host_port_reg_ofs      = 0x108,
 444         .hw_stats_reg_ofs       = 0x900,
 445         .bd_ram_ofs             = 0x2000,
 446         .mac_control            = (1 << 5),
 447         .control                = cpsw_control,
 448         .host_port_num          = 0,
 449         .version                = CPSW_CTRL_VERSION_2,
 450 };
 451
 452 int board_eth_init(bd_t *bis)
 453 {
 454         int rv;
 455         uint8_t mac_addr[6];
 456         uint32_t mac_hi, mac_lo;
 457
 458         /* try reading mac address from efuse */
 459         mac_lo = readl(&cdev->macid0l);
 460         mac_hi = readl(&cdev->macid0h);
 461         mac_addr[0] = mac_hi & 0xFF;
 462         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 463         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 464         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 465         mac_addr[4] = mac_lo & 0xFF;
 466         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 467
 468         if (!getenv("ethaddr")) {
 469                 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 470                 if (is_valid_ether_addr(mac_addr))
 471                         eth_setenv_enetaddr("ethaddr", mac_addr);
 472         }
 473
 474         mac_lo = readl(&cdev->macid1l);
 475         mac_hi = readl(&cdev->macid1h);
 476         mac_addr[0] = mac_hi & 0xFF;
 477         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 478         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 479         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 480         mac_addr[4] = mac_lo & 0xFF;
 481         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 482
 483         if (!getenv("eth1addr")) {
 484                 if (is_valid_ether_addr(mac_addr))
 485                         eth_setenv_enetaddr("eth1addr", mac_addr);
 486         }
 487
 488         if (board_is_eposevm()) {
 489                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 490                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 491                 cpsw_slaves[0].phy_addr = 16;
 492         } else {
 493                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 494                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 495                 cpsw_slaves[0].phy_addr = 0;
 496         }
 497
 498         rv = cpsw_register(&cpsw_data);
 499         if (rv < 0)
 500                 printf("Error %d registering CPSW switch\n", rv);
 501
 502         return rv;
 503 }
 504 #endif